A composable, energy-managed, real-time MPSOC platform

Abstract

Abstract-Multi-processors systems on chip (MPSOC) platforms emerged in embedded systems as hardware solutions to support the continuously increasing functionality and performance demands in this domain. Such a platform has to execute a mix of applications with diverse performance and timing constraints, i.e., real-time or non-real-time, thus different application schedulers should co-exist on an MPSOC. Moreover, applications share many MPSOC resources, thus their timing depends on the arbitration at these resources. Arbitration may create inter-application dependencies, e.g., the timing of a low priority application depends on the timing of all higher priority ones. Application inter-dependencies make the functional and timing verification and the integration process harder. This is especially problematic for real-time applications, for which fulfilling the time-related constraints should be guaranteed by construction. Moreover, energy and power management, commonly employed in embedded systems, make this verification even more difficult. Typically, energy and power management involves scaling the resources operating point, which has a direct impact on the resource performance, thus influences the application time behaviour. Finally, a small change in one application leads to the need to re-verify all other applications, incurring a large effort. Composability is a property meant to ease the verification and integration process. A system is composable if the functionality and the timing behaviour of each application is independent of other applications mapped on the same platform. Composability is achieved by utilising arbiters that ensure applications independence. In this paper we present the concepts behind a composable, scalable, energy-managed MPSOC platform, able to support different real-time and nonreal time schedulers concurrently, and discuss its advantages and limitations.

Power Minimisation for Real-Time Dataflow Applications

“…We evaluate the practicality of our technique by apply- ing it to an actual tile-based, Multiprocessor SoC (MPSoC), hardware platform implementation, that uses per-tile DVFS hardware, as described in [11]. We apply our technique to both a synthetic real-time dataflow application example, as illustrated in Figure 1, and a WLAN 802.11a, real-time, dataflow application that can be found in [12] and illustrated in Figure 2.…”

“…For this purpose we use the platform template described in [11]. The platform template uses a tile based hardware architecture, with tiles connected using a predictable hardware interconnect, such as those described in [17]- [19].…”

“…One of the µBlaze tiles acts as the host tile, configuring the NoC and monitoring status information received from the other tiles. The rest of the tiles consist of a µBlaze processing core connected to a programmable timer that sends an interrupt after its programmed time delay and a VFS unit, as described in [11], [21]. The DVFS module provides 17 equidistant power levels from a 0 MHz clock gate state up to the frequency provided by the system clock, as illustrated in Figure 4.…”

“…The DVFS module provides 17 equidistant power levels from a 0 MHz clock gate state up to the frequency provided by the system clock, as illustrated in Figure 4. As per the scheme described in [11] DMA's are used to transfer data between tiles, with at least one DMA per application to ensure application level predictability. Predictability is also important on the processor.…”

“…To facilitate this our platform uses the CompOSe [22] Real-time Operating System (RTOS) with Time Division Multiplexed (TDM) scheduling to allocate processing time to an application guaranteeing that the application is scheduled for a fixed amount of time in the TDM period. We achieve this as described in [11] using a hardware timer connected to each processor that is programmed to interrupt the processor after fixed intervals allowing running applications to be swapped out by the RTOS in a fixed length time slice, which we refer to as the OS time slice. Importantly, during the application's allotted time no interrupt can arrive apart from that associated with the TDM scheduler signalling the end of its scheduled time.…”