Memory Controllers for Real-Time Embedded Systems

Åkesson, Benny; Goossens, Kees

doi:10.1007/978-1-4419-8207-0

Cited by 26 publications

(37 citation statements)

References 49 publications

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“…This article reasons about real-time memory controller performance in terms of memory patterns, as defined in [17]. A memory pattern is a small series of scheduled SDRAM commands with known length and function.…”

Section: Memory Patternsmentioning

confidence: 99%

“…The worst-case data bus utilization on the SDRAM interface can be determined for a given pattern set, as shown in [17]. We refer to this metric as memory efficiency (see Figure 1).…”

Section: Memory Patternsmentioning

confidence: 99%

“…a) shows a single burst access, b) demonstrates bank interleaving, d) combines bank interleaving with an increased burst count per bank. Efficiencies are derived based on the algorithm in [17], which also takes read/write switches and refresh overhead into account.…”

Section: Burst Groupingmentioning

confidence: 99%

“…The ADDACTANDRW function schedules an activate command using ADDACT before the first burst to a bank (lines [17][18]. Additionally, it schedules the read/write commands as soon as possible (lines 16,19).…”

Section: Pattern Generationmentioning

confidence: 99%

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Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling

Goossens

Chandrasekar

Åkesson

et al. 2016

IEEE Trans. Comput.

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Abstract-Real-time safety-critical systems should provide hard bounds on an applications' performance. SDRAM controllers used in this domain should therefore have a bounded worst-case bandwidth, response time, and power consumption. Existing works on real-time SDRAM controllers only consider a narrow range of memory devices, and do not evaluate how their schedulers' performance varies across memory generations, nor how the scheduling algorithm influences power usage. The extent to which the number of banks used in parallel to serve a request impacts performance is also unexplored, and hence there are gaps in the tool set of a memory subsystem designer, in terms of both performance analysis, and configuration options. This article introduces a generalized close-page memory command scheduling algorithm that uses a variable number of banks in parallel to serve a request. To reduce the schedule length for DDR4 memories, we exploit bank grouping through a pairwise bank-group interleaving scheme. The algorithm is evaluated using an ILP formulation, and provides schedules of optimal length for most of the considered LPDDR, DDR2, DDR3, LPDDR2, LPDDR3 and DDR4 devices. We derive the worst-case bandwidth, power and execution time for the same set of devices, and discuss the observed trade-offs and trends in the scheduler-configuration design space based on these metrics, across memory generations.

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Section: Memory Patternsmentioning

confidence: 99%

“…The worst-case data bus utilization on the SDRAM interface can be determined for a given pattern set, as shown in [17]. We refer to this metric as memory efficiency (see Figure 1).…”

Section: Memory Patternsmentioning

confidence: 99%

Section: Burst Groupingmentioning

confidence: 99%

Section: Pattern Generationmentioning

confidence: 99%

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Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling

Goossens

Chandrasekar

Åkesson

et al. 2016

IEEE Trans. Comput.

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“…These guarantees are conservative and simpler than those presented in [14], for ease of understanding. We then analyze the impact of the conservative, aggressive and speculative power-down strategies on these bounds.…”

Section: Impact On Latency-bandwidth Boundsmentioning

confidence: 99%

Run-time power-down strategies for real-time SDRAM memory controllers

Chandrasekar

Åkesson

Goossens

2012

Proceedings of the 49th Annual Design Automation Conference

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Powering down SDRAMs at run-time reduces memory energy consumption significantly, but often at the cost of performance. If employed speculatively with real-time memory controllers, power-down mechanisms could impact both the guaranteed bandwidth and the memory latency bounds. This calls for power-down strategies that can hide or bound the performance loss, making run-time memory power-down feasible for real-time applications.In this paper, we propose two such strategies that reduce memory energy consumption and yet guarantee realtime memory performance. One provides significant energy savings without impacting the guaranteed bandwidth and latency bounds. The other provides higher energy savings with marginally increased latency bounds, while still preserving the guaranteed bandwidth provided by real-time memory controllers. We also present an algorithm to select the most energy-efficient power-down mode at run-time. We experimentally evaluate the two strategies at run-time by executing four media applications concurrently on a real-time MPSoC platform and show memory energy savings of 42.1% and 51.3% for the two strategies, respectively.

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Reconfigurable Real-Time Memory Controller Architecture

et al. 2016

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The purpose of this chapter is to set the stage on which the rest of this book plays out. We describe the technology that we work with, in the form of the SDRAM chips that external companies produce for us (and the rest of the world) in Sect. 2.1. Because, the same SDRAM chips are used by everyone, it is not surprising that most memory controllers, i.e., the interfaces that interact with these chips, have at least the same high-level structure, as introduced earlier in Sect. 1.2. For the sake of efficiency, the proverbial wheel tends to be invented only a few times before the interested community settles for a design that works in most cases. Further improvements are driven by the needs of specific application areas and the gradual evolution of the surrounding actors and requirements. This book focuses on the area of mixed timecriticality systems, and uses an existing SDRAM controller template for real-time systems, the pattern-based controller [1], as its starting point. The properties of this controller are introduced in Sect. 2.2.The story continues with a detailed description of our novel reconfigurable memory controller architecture in Sect. 2.3. It partially concerns the introduction of concepts and structures used in the controller, and touches upon some of the real-time aspects that are influenced by its structure and implementation. This controller is the framework on which the other contributions in this book are pinned. The memory patterns we generate in Chap. 3 are stored within this controller. The analysis from Chap. 4 and the trade-offs we describe in Chap. 5 apply to memory controllers that follows the architecture template we describe here, and the conservative open-page policy in Chap. 6 is implemented on a slightly modified version of the same template. The embedded reconfiguration hardware enables the controller to adapt to different use-cases as we describe in Chap. 7.In Sect. 2.4, we derive a worst-case performance model for this memory controller architecture, based on a Latency-rate (LR) server abstraction. This performance model applies to many well known arbiters and can be used in frameworks that enable system-level analysis. We then continue with a discussion on the implementation of a hardware instance on Field Programmable Gate Array (FPGA) in Sect. 2.5, which demonstrates that this memory controller is not only conceptually sound, but really works when it is connected to a real SDRAM module and integrated SDRAMSDRAM is an extremely popular type of memory. DRAMExchange (a market analyst) reports that in February 2015 alone, 2.4 billion 2 gibibit (2 30 ) equivalent units were produced worldwide [3], for a total capacity of 5.16 exabits. This amounts to a production rate of 267 GB/s, 1 a relatively modest "bandwidth" that about 100 combined contemporary SDRAM devices (single chips) could easily deliver in the worst case, as we later show in Chap. 5.SDRAM is volatile and used as temporary data storage, similarly to caches or Static Random-Access Memory (SRAM) memories. It only stores d...

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Memory Controllers for Real-Time Embedded Systems

Cited by 26 publications

References 49 publications

Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling

Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling

Run-time power-down strategies for real-time SDRAM memory controllers

Reconfigurable Real-Time Memory Controller Architecture

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