A Comprehensive Delay Model for CMOS CML Circuits

Abstract

MOS-transistor-based current-mode logic (CML)-type (MCML) circuits in high-speed circuit applications often operate as low-swing analog circuits rather than fully switched digital circuits. At these high-speed operations, the effect of the finite input signal slope on the delay of MCML gates significantly increases mainly due to incomplete current steering. Hence, for such cases, the conventional RC delay model which is based on ideal step input assumption fails to track the delay of MCML circuits with errors as high as 40% when a design is optimized for high-speed. In this paper, a comprehensive delay model is proposed that accurately predicts the delay of MCML circuits for all types of operation from low-speed and fully switched to high-speed and low-swing applications by including the input slope effect (ISE) into the conventional RC delay model. Furthermore, the proposed model is extended to multilevel complex logic gates without losing the general RC delay model format. Theoretical results are compared with Spice simulations in a 0.13-m CMOS technology. Results show that the error in delay of the proposed model is less than 20% for all practical designs. The proposed model is still sufficiently tractable to be use in back-of-envelope calculations that achieve close-to-optimum solutions without running extensive parametric simulations. In addition to the achieved accuracy and preserved simplicity, the proposed model enhances the intuitive understanding of MCML gates that simple RC delay model fails to provide.

Stabilization of Discrete-Time Systems With Multiple Actuator Delays and Saturations

“…where is the unique positive definite solution to the following parametric discrete-time algebraic Riccati equation (DARE) (23) in which . Properties of solutions to the DARE (23) are summarized in Lemma 1 in the Appendix.…”

Current and Emerging Trends in the Design of Digital-to-Analog Converters

“…This in turn is seen to be limited by the device transit or cut-off frequency (f T ) for a given process [11]. In current-mode circuits, a general rule of thumb is to restrict the transistor switching speed to lesser than f T =20 [12].…”

“…Figure 3.19a illustrates the switching action in a current-steering cell, where the data signal at the gate switches between voltage levels separated by DV IN , with a rise time t R . Using the model described in [12], the delay of a current-mode switching cell can be expressed as All the above parameters are inter-dependent. For instance, a large value of DV IN improves the switching characteristics.…”

A single-event upset hardening technique for high speed MOS Current Mode Logic

“…An alternative to CMOS in these scenarios is MOS Current Mode Logic (MCML). MCML is a popular logic style in high-speed systems, especially when analog and digital circuits are integrated onto the same die [4]. MCML has been used in multi-GHz communication systems such as high-speed cross-point switches for networks (LAN/WAN) [5], RF applications (PLL, pre-scalers, clock recovery circuits) [6]- [7] and very high-speed buffers/links [8].…”