A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory

Zhang, Rui; Yang, Kexin; Liu, Zhaocheng; Liu, Taizhi; Cai, Wenshan; Milor, Linda

doi:10.1109/tvlsi.2021.3056674

Cited by 6 publications

(4 citation statements)

References 66 publications

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“…BlueIO's linear scalability concerning the number of CPUs and I/O devices was shown by our VLSI and FPGA implementations, which are analyzed in this research from a hardware consumption perspective expressed [25]. Comprehensive framework (CF) for Given different operating conditions, configurations, supply voltage scaling, and aging processes, an SRAM cache's availability and reliability will degrade with time described [26]. Non-Volatile Memory Technology for last-level caches that use SRAM, STT-MRAM, and SOT-MRAM technologies reported [27].…”

Section: Background Studymentioning

confidence: 99%

Improved Smart Memory Design Structure and Processor Framework for Embedded System

2024

Preprint

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Digital cameras, sensor technologies and diagnostic imaging technologies are recent additions to the ever-growing list of embedded systems applications. A substantial number of activities in current multiprocessor embedded devices are executed on common processors, and associated complicated connections are handled through shared communication networks. Non-volatile, solid-state reliable, inexpensive and high-density NAND flash memory has quickly become an essential component in embedded systems. Embedded systems designers face a formidable obstacle in the design limits imposed by embedded systems, compounded by the rising need to reduce costs and time-to-market. Hence this paper, Effective Programmable Model (EPM) with NAND flash memory has been proposed for compute-intensive embedded applications. To keep delivery costs down, the processor design uses instruction registers, while a hierarchical and decentralized data register structure is used to transport data. Instruction registers record the reuse and localization of instructions in low-cost, close-to-functional-units storage structures. A method for reducing hold power dissipation is provided by the SRAM architecture that has been presented in this paper. Using NAND storage for the code's execution space proved that our suggested architecture would work in a practical embedded setting. These structural modifications allow for better improvement in energy efficiency over previously possible embedded processors. Our proposed method achieves a high-performance ratio of 98.7%, a less throughput ratio of 16.4% and an error rate of 18.3% compared to other methods.

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Section: Background Studymentioning

confidence: 99%

Improved Smart Memory Design Structure and Processor Framework for Embedded System

2024

Preprint

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“…Any abnormal function within a chip module can lead to system failure, emphasizing the need for robust chip verification methods. Among the critical modules in a processor chip, the Cache [1,2] plays a significant role by storing frequently accessed instructions or data. It possesses features such as a relatively small capacity and high speed.…”

Section: Introductionmentioning

confidence: 99%

“…Under normal circumstances, the current item is released when it is accessed successfully. (2) L2 Cache returns data in an out-of-order manner: During a sequential branch fetch, the instruction Cache sends two consecutive requests to the L2 Cache. Depending on the situation in the L2 Cache, it may not return the requested data in the expected order.…”

mentioning

confidence: 99%

A Universal-Verification-Methodology-Based Testbench for the Coverage-Driven Functional Verification of an Instruction Cache Controller

Liu,

Xu,

Chen

et al. 2023

Electronics

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The Cache plays an important role in computer architecture by reducing the access time of the processor and improving its performance. The hardware design of the Cache is complex and it is challenging to verify its functions, so the traditional Verilog-based verification method is no longer applicable. This paper proposes a comprehensive and efficient verification testbench based on the SystemVerilog language and universal verification methodology (UVM) for an instruction Cache (I-Cache) controller. Corresponding testcases are designed for each feature of the I-Cache controller and automatically executed using a python script on an electronic design automation (EDA) tool. After simulating a large number of testcases, the statistics reveal that the module’s code coverage is 99.13%. Additionally, both the function coverage and the assertion coverage of the module reach 100%. Our results demonstrate that these coverage metrics meet the requirements and ensure the thoroughness of function verification. Furthermore, the established verification testbench exhibits excellent scalability and reusability, making it easily applicable to higher-level verification scenarios.

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“…These phenomena lead to malfunction in circuits. From BTI to BEOL TDDB, there are numerous studies for their impact on device, circuit, and system performance and reliability [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30], but they are not the topic discussed here. In this paper, our attention is focused on recent progress in physics-based modeling of EM in on-chip interconnects.…”

Section: Introductionmentioning

confidence: 99%

Recent Progress in Physics-Based Modeling of Electromigration in Integrated Circuit Interconnects

2022

Self Cite

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The advance of semiconductor technology not only enables integrated circuits with higher density and better performance but also increases their vulnerability to various aging mechanisms which occur from front-end to back-end. Analysis on the impact of aging mechanisms on circuits’ reliability is crucial for the design of reliable and sustainable electronic systems at advanced technology nodes. As one of the most crucial back-end aging mechanisms, electromigration deserves research efforts. This paper introduces recent studies on physics-based modeling of electromigration aging of on-chip interconnects. At first, the background of electromigration is introduced. The conventional method and physics-based modeling for electromigration are described. Then studies on how electromigration affects powers grids and signal interconnects are discussed in detail. Some of them focus on the comprehensiveness of modeling methodology, while others aim at the strategies for improving computation accuracy and speed and the strategies for accelerating/decelerating aging. Considering the importance of electromigration for circuit reliability, this paper is dedicated to providing a review on physics-based modeling methodologies on electromigration and their applications for integrated circuits interconnects.

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A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory

Cited by 6 publications

References 66 publications

Improved Smart Memory Design Structure and Processor Framework for Embedded System

Improved Smart Memory Design Structure and Processor Framework for Embedded System

A Universal-Verification-Methodology-Based Testbench for the Coverage-Driven Functional Verification of an Instruction Cache Controller

Recent Progress in Physics-Based Modeling of Electromigration in Integrated Circuit Interconnects

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