A Comprehensive Gate and Drain Trapping/Detrapping Noise Model and its Implications for Thin-Dielectric MOSFETs

Asanovski, Ruben; Palestri, Pierpaolo; Caruso, Enrico; Selmi, L.

doi:10.1109/ted.2021.3104790

Cited by 10 publications

(8 citation statements)

References 41 publications

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“…f Additionally, noise at different frequencies comes from traps located at different positions. 3)] that based on the CNF theory, 39,41) and is in good agreement with simulatied results. As Vg increases, the noise contribution from GD traps drops sharply, while those from BOX traps cannot be ignored even at high Vg.…”

Section: Dependence Of Noise On the Trap's Energy And Positionsupporting

confidence: 84%

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Simulation study of trap-induced noise characteristics in FDSOI MOSFETs

Xu,

Fan,

Sun

et al. 2024

Jpn. J. Appl. Phys.

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The trap-induced noise characteristics of fully-depleted SOI (FDSOI) MOSFETs with Ultra-Thin Body and Buried Oxide (UTBB) are essential for high-performance applications. However, accurate noise modeling and traps identification of the device remains challenging. In this work, we investigate the noise characteristics of FDSOI MOSFETs arising from traps in both the gate dielectric (GD) and the buried oxide (BOX). By using TCAD tool, we examine the noise generated by traps at various energy levels and spatial positions in GD and BOX under different biases. The simulation results reveal that traps in GD and BOX exhibit distinctly different behaviors as Vg increases, providing insights for identifying traps from noise measurement results.

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Section: Dependence Of Noise On the Trap's Energy And Positionsupporting

confidence: 84%

“…This derivation considers effective capacitance, transconductance, and trap concentration. 39) To align with simulation method, we omitted the integral in the energy level direction, which allows us to represent the noise PSD for traps at a single energy level and a specific spatial position.…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

Simulation study of trap-induced noise characteristics in FDSOI MOSFETs

Xu,

Fan,

Sun

et al. 2024

Jpn. J. Appl. Phys.

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“…The 1/f noise in the CNFs regime (α sc µ eff C ox I D /g m ≪ 1) is proportional to the effective trap density N BT inside the dielectrics This quantity represents an effective trap density since it does not take into account the spatial sensitivity of noise to the dielectric trap fluctuations and the trapping/detrapping events involving the gate electrode [20], [21], [22]. However, despite these limitations, S vg in the CNF regime can serve as a monitor of the quality of gate dielectrics, particularly when comparing devices with similar gate-stacks (i.e., same gate metals and as-deposited dielectric thicknesses), as it is in our study.…”

Section: B 1/f Noisementioning

confidence: 99%

Characterization and Advanced Modeling of Dielectric Defects in Low-Thermal Budget RMG MOSFETs Using 1/f Noise Analysis

Asanovski,

Arimura,

de Marneffe

et al. 2024

IEEE Trans. Electron Devices

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This study presents a comprehensive investigation of defects in the gate-stack of low-thermal budget replacement metal gate (RMG) MOSFETs treated with novel dielectric passivation techniques using 1/f noise characterization and advanced modeling. This research demonstrates that MOSFETs with gate-stacks treated with atomic hydrogen (H*) and oxygen (O*) (T < 450 • C) yield 1/f noise levels comparable to those of high-thermal budget devices. We also demonstrate that the noise of both pMOSFETs and nMOSFETs mainly originates from defects in the SiO 2 interfacial layer (IL). In addition, accurate modeling of 1/f noise provides useful insights into the dielectric defect densities before and after passivation. Notably, the contribution of O-vacancies in HfO 2 to 1/f noise appears negligible, whereas it is very important for positive bias temperature instabilities (PBTIs). The results confirm the effectiveness of H* and O* treatments in reducing the electrically active dielectric defects while contributing to a better understanding of the underlying passivation mechanisms.

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“…To check if these states can be responsible for the 1/f noise at cryogenic temperatures, we calculate S vg for the CNF region according to the following expression [25], [26]:…”

Section: Relationship Between Band Tail States and 1/f Noisementioning

confidence: 99%

“…It is equal to 1 when considering traps inside the channel (such as the band tail states), while it assumes a more complex form for dielectric traps in a gate-stack with an interlayer (see Table I in [25]). Considering an nMOS, we attempt to reproduce the effect of band tail states in the noise by inserting a trap distribution in the silicon channel with an exponential distribution in energy and space…”

Section: Relationship Between Band Tail States and 1/f Noisementioning

confidence: 99%

Understanding the Excess 1/f Noise in MOSFETs at Cryogenic Temperatures

Asanovski

Grill

Franco

et al. 2023

IEEE Trans. Electron Devices

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Characterization, modeling, and development of cryo-temperature CMOS technologies (cryo-CMOS) have significantly progressed to help overcome the interconnection bottleneck between qubits and the readout interface in quantum computers. Nevertheless, available compact models still fail to predict the deviation of 1/f noise from the expected linear scaling with temperature (T ), referred to as "excess 1/f noise," observed at cryogenic temperatures. In addition, 1/f noise represents one of the main limiting factors for the decoherence time of qubits. In this article, we extensively characterize low-frequency noise on commercial 28-nm CMOS and on research-grade Ge-channel MOSFETs at temperatures ranging from 370 K down to 4 K. Our investigations exclude electron heating and bulk dielectric defects as possible causes of the excess 1/f noise at low temperatures. We show further evidence for a strong correlation between the excess 1/f noise and the saturation of the subthreshold swing (SS) observed at low temperatures. The most plausible cause of the excess noise is found in band tail states in the channel acting as additional capture/emission centers at cryogenic temperatures.

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A Comprehensive Gate and Drain Trapping/Detrapping Noise Model and its Implications for Thin-Dielectric MOSFETs

Cited by 10 publications

References 41 publications

Simulation study of trap-induced noise characteristics in FDSOI MOSFETs

Simulation study of trap-induced noise characteristics in FDSOI MOSFETs

Characterization and Advanced Modeling of Dielectric Defects in Low-Thermal Budget RMG MOSFETs Using 1/f Noise Analysis

Understanding the Excess 1/f Noise in MOSFETs at Cryogenic Temperatures

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