In this work, we present a comprehensive theoretical and experimental study of quantum confinement in layered platinum diselenide (PtSe 2 ) films as a function of film thickness. Our electrical measurements, in combination with density functional theory calculations, show distinct layer-dependent semimetal-to-semiconductor evolution in PtSe 2 films, and highlight the importance of including van der Waals interactions, Green's function calibration, and screened Coulomb interactions in the determination of the thickness-dependent PtSe 2 energy gap. Large-area PtSe 2 films of varying thickness (2.5-6.5 nm) were formed at 400°C by thermally assisted conversion of ultra-thin platinum films on Si/SiO 2 substrates. The PtSe 2 films exhibit p-type semiconducting behavior with hole mobility values up to 13 cm 2 /V·s. Metal-oxide-semiconductor field-effect transistors have been fabricated using the grown PtSe 2 films and a gate field-controlled switching performance with an I ON /I OFF ratio of >230 has been measured at room temperature for a 2.5-3 nm PtSe 2 film, while the ratio drops to <2 for 5-6.5 nm-thick PtSe 2 films, consistent with a semiconductingto-semimetallic transition with increasing PtSe 2 film thickness. These experimental observations indicate that the low-temperature growth of semimetallic or semiconducting PtSe 2 could be integrated into the back-end-of-line of a silicon complementary metaloxide-semiconductor process.npj 2D Materials and Applications (2019) 3:33 ; https://doi.

Border traps and interface traps in HfO2/few-layer MoS2 top-gate stacks are investigated by C–V characterization. Frequency dependent C–V data shows dispersion in both the depletion and accumulation regions for the MoS2 devices. The border trap density is extracted with a distributed model, and interface traps are analyzed using the high-low frequency and multi-frequency methods. The physical origins of interface traps appear to be caused by impurities/defects in the MoS2 layers, performing as band tail states, while the border traps are associated with the dielectric, likely a consequence of the low-temperature deposition. This work provides a method of using multiple C–V measurements and analysis techniques to analyze the behavior of high-k/TMD gate stacks and deconvolute border traps from interface traps.

The advent of two-dimensional materials has opened a plethora of opportunities in accessing ultrascaled device dimensions for future logic and memory applications. In this work, we demonstrate that a single layer of large-area chemical vapor deposition-grown molybdenum disulfide (MoS2) sandwiched between two metal electrodes can be tuned to show multilevel nonvolatile resistive memory states with resistance values separated by 5 orders of magnitude. The switching process is unipolar and thermochemically driven requiring significant Joule heating in the reset process. Temperature-dependent electrical measurements coupled with semiclassical charge transport models suggest that the transport in these devices varies significantly in the initial (pristine) state, high resistance state, and low resistance state. In the initial state, the transport is a one-step direct tunneling (at low voltage biases) and Fowler Nordeim tunneling (at higher bias) with an effective barrier height of 0.33 eV, which closely matches the Schottky barrier at the MoS2/Au interface. In the high resistive state, trap-assisted tunneling provides a reasonable fit to experimental data for a trap height of 0.82 eV. Density functional theory calculations suggest the possibility of single- and double-sulfur vacancies as the microscopic origins of these trap sites. The temperature-dependent behavior of the set and reset process are explained by invoking the probability of defect (sulfur vacancy) creation and mobility of sulfur ions. Finally, conductive atomic force microscopy measurements confirm that the multifilamentary resistive memory effects are inherent to a single-crystalline MoS2 triangle and not necessarily dependent on grain boundaries. The insights suggested in this work are envisioned to open up possibilities for ultrascaled, multistate, resistive memories for next-generation digital memory and neuromorphic applications.

We present and thoroughly compare band-structures computed with density functional theory,\ud tight-binding, k p and non-parabolic effective mass models. Parameter sets for the non-parabolic C,\ud the L and X valleys and intervalley bandgaps are extracted for bulk InAs, GaAs and InGaAs. We then\ud consider quantum-wells with thickness ranging from 3 nm to 10 nm and the bandgap dependence on\ud film thickness is compared with experiments for In0:53Ga0:47As quantum-wells. The impact of the\ud band-structure on the drain current of nanoscale MOSFETs is simulated with ballistic transport models,\ud the results provide a rigorous assessment of III–V semiconductor band structure calculation methods and\ud calibrated band parameters for device simulations

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