Performance projection of III-V ultra-thin-body, FinFET, and nanowire MOSFETs for two next-generation technology nodes

Rau, Martin; Caruso, Enrico; Lizzit, Daniel; Palestri, Pierpaolo; Esseni, D.; Schenk, Andreas; Selmi, L.; Luisier, Mathieu

doi:10.1109/iedm.2016.7838515

Cited by 31 publications

(22 citation statements)

References 8 publications

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“…The calibration of the material-related properties (metal workfunction, effective channel electron mobility, saturation velocity) for InGaAs and Si devices is performed separately. For all the investigated InGaAs devices (DG-UTB and FinFET at both nodes), it is possible to correctly reproduce the transfer characteristics in both linear and saturation regimes as obtained by higher-order transport models [26] with a unique set of QDD parameters, see Figs. 2-4 (where VT and short-channel parameters are also shown).…”

Section: A Calibrationmentioning

confidence: 99%

Threshold Voltage Statistical Variability and Its Sensitivity to Critical Geometrical Parameters in Ultrascaled InGaAs and Silicon FETs

Zagni

Puglisi

Verzellesi

et al. 2017

IEEE Trans. Electron Devices

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We investigate the statistical variability of the threshold voltage and its sensitivity to critical geometrical parameters in ultrascaled In0.53Ga0.47As and Si MOSFETs by means of 3-D quantum-corrected drift-diffusion simulations. Dual-gate ultrathin-body and FinFET device structures are analyzed for both channel materials. To assess the variability and sensitivity effects also from the scaling perspective, we consider devices belonging to two technological nodes with gate lengths 15 and 10.4 nm, designed according to International Technology Roadmap for Semiconductors (ITRS) specifications. Variability sources included in our analysis are random-dopant fluctuation, work-function fluctuation (WFF), as well as body- and gate-line-edge roughness (LER). Sensitivity to critical geometrical parameters is assessed by varying gate length, channel thickness, and oxide thickness. Results point out the major detrimental effect of WFF and Body-LER for InGaAs FETs, whereas WFF dominates in Si counterparts. Moreover, the sensitivity analysis shows that control over gate length and channel thickness in the InGaAs technology is fundamental in order to keep variability within tolerable values. Scaling of the InGaAs technology highlights the importance of abiding to ITRS projections regarding LER control improvement. Furthermore, a tight channel thickness control is required in ultrascaled devices due to the large sensitivity of the threshold voltage to the channel thickness combined with increased variability

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Section: A Calibrationmentioning

confidence: 99%

Threshold Voltage Statistical Variability and Its Sensitivity to Critical Geometrical Parameters in Ultrascaled InGaAs and Silicon FETs

Zagni

Puglisi

Verzellesi

et al. 2017

IEEE Trans. Electron Devices

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“…However, FinFETs will struggle to keep control of device electrostatics in future generations of complementary metaloxide-semiconductor (CMOS) technology [1]. The eventual changeover to different architectures like nanosheet (NS) [2]- [5] or nanowire (NW) FETs [6], [7], and/or to different channel materials like Ge or III-Vs [8]- [10] requires thorough ground work. Therefore, physically-based 3D simulations play an essential role to benchmark the most promising candidates.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, physically-based 3D simulations play an essential role to benchmark the most promising candidates. Although many works already compared FinFET and NW FET architectures [2], [10]- [12], there are fewer that include a predictive physically based comparison of FinFET, NS and NW FETs [6], [13], [14]. These works The associate editor coordinating the review of this manuscript and approving it for publication was Sun Junwei .…”

Section: Introductionmentioning

confidence: 99%

Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

et al. 2020

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Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length (L G) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrödinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to L G of 16 nm offering a larger on-current (I ON) and slightly better sub-threshold characteristics. Below L G of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current (I OFF), and the largest I ON /I OFF ratio out of the three architectures. However, the NW FET suffers from early I ON saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device body.

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“…The aggressive downscaling of CMOS transistors demands for design solutions to obtain large drive currents at small supply voltage and preserve low leakage currents. The possible options for technology improvement include the reduction of source/drain series resistance that is responsible for a degradation of the transistor on-current by 30%-40%, 1,2 the use of semiconductors alternative to silicon, [2][3][4][5][6][7][8] the introduction of stressors, 9,10 and the development of device architectures beyond planar FETs such as multi-gate FETs (MuGFETs). 7,9,11 In particular, for CMOS generations beyond the 7-nm node, gate-all-around (GAA) nanowire FETs appear to be the most promising architecture.…”

Section: Introductionmentioning

confidence: 99%

“…7,9,11 In particular, for CMOS generations beyond the 7-nm node, gate-all-around (GAA) nanowire FETs appear to be the most promising architecture. 1,2,5,[12][13][14][15] However, nanowire transistors still face significant challenges and, due to the high surface-tovolume ratio, the performance of these devices is strongly influenced by surface roughness (SR) and interface defects. [16][17][18][19][20][21] In this framework, an accurate description of interface effects in order to predict the device performance is required, and the aim of this work is to present a new model for SR scattering in MuGFETs with arbitrary cross-sections.…”

Section: Introductionmentioning

confidence: 99%

Improved surface-roughness scattering and mobility models for multi-gate FETs with arbitrary cross-section and biasing scheme

Lizzit

Badami

Specogna

et al. 2017

Journal of Applied Physics

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We present a new model for surface roughness (SR) scattering in n-type multi-gate FETs (MuGFETs) and gate-all-around nanowire FETs with fairly arbitrary cross-sections, its implementation in a complete device simulator, and the validation against experimental electron mobility data. The model describes the SR scattering matrix elements as non-linear transformations of interface fluctuations, which strongly influences the root mean square value of the roughness required to reproduce experimental mobility data. Mobility simulations are performed via the deterministic solution of the Boltzmann transport equation for a 1D-electron gas and including the most relevant scattering mechanisms for electronic transport, such as acoustic, polar, and non-polar optical phonon scattering, Coulomb scattering, and SR scattering. Simulation results show the importance of accounting for arbitrary cross-sections and biasing conditions when compared to experimental data. We also discuss how mobility is affected by the shape of the cross-section as well as by its area in gate-all-around and tri-gate MuGFETs. © 2017 Author(s)

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Performance projection of III-V ultra-thin-body, FinFET, and nanowire MOSFETs for two next-generation technology nodes

Cited by 31 publications

References 8 publications

Threshold Voltage Statistical Variability and Its Sensitivity to Critical Geometrical Parameters in Ultrascaled InGaAs and Silicon FETs

Threshold Voltage Statistical Variability and Its Sensitivity to Critical Geometrical Parameters in Ultrascaled InGaAs and Silicon FETs

Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

Improved surface-roughness scattering and mobility models for multi-gate FETs with arbitrary cross-section and biasing scheme

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