Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

Abstract

Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length (L G) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrödinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to L G of 16 nm offering a larger on-current (I ON) and slightly better sub-threshold characteristics. Below L G of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current (I OFF), and the largest I ON /I OFF ratio out of the three architectures. However, the NW FET suffers from early I ON saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device body.

Simulations of Statistical Variability in n-Type FinFET, Nanowire, and Nanosheet FETs

“…1(a)-(c) present 3D schemes of the three device architectures and show their physical dimensions. The 12 nm NS FET structure is designed after the experimental device reported in [6] and it was previously validated in [5]. Because doping profiles in the source/drain and channel regions are typically unknown, the profiles are determined from the experimental I-V characteristics in the sub-threshold by a reverse engineering process [5], [14] (see resulting values in Fig.…”

“…Gate-allaround (GAA) nanowire (NW) FETs are currently considered as one of the strongest contenders to replace the FinFETs because of their superior gate control [3] but, their adoption implies a substantial change in the fabrication processes [4]. The GAA nanosheet (NS) FETs have been proposed as an intermediate step between both architectures due to a slightly better performance than the FinFETs [5] while reusing, with minimal changes [6], its fabrication process.…”

Evaluation of Device Fabrication from FET to CFET: A Review

“…Research done at IMEC has proved that a nanosheet device shows a 10 % speed gain (at constant power) and a 24 % power reduction (at constant speed) 06030-7 compared to a FinFET [40]. Contrary to the nanosheet device, the sheets are now controlled by a forked gate structure as shown in Fig.…”

Simulation and Modeling of Novel Electronic Device Architectures with NESS (Nano-Electronic Simulation Software): A Modular Nano TCAD Simulation Framework

“…Therefore, new super-scalable FET architectures are intensively researched. The most likely winner is the NWT, thanks to the all-around gate and the possibility for stacking NWTs [6,7].…”

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