Simulations of Statistical Variability in n-Type FinFET, Nanowire, and Nanosheet FETs

Abstract

Four sources of variability, metal grain granularity (MGG), line-edge roughness (LER), gate-edge roughness (GER), and random discrete dopants (RDD), affecting the performance of state-of-the-art FinFET, nanosheet (NS), and nanowire (NW) FETs, are analysed via our in-house 3D finite-element driftdiffusion/Monte Carlo simulator that includes 2D Schrödinger equation quantum corrections. The MGG and LER are the sources of variability that influence device performance of the three multi-gate architectures the most. The FinFET and the NS FET are similarly affected by the MGG variations with threshold voltage and on-current standard deviations significantly lower (at least 20 %) than those of the NW FET. The LER variability has a negligible influence in the NS FET performance with σVT values around 12 and 42 times lower than those of the FinFET and the NW FET. The three architectures are equally affected by the RDD (σVT = 8 mV) and minimally influenced by the GER (σVT ≈ 4 mV). The variability of NS FETs makes them strong candidates to replace FinFETs.

Pelgrom-Based Predictive Model to Estimate Metal Grain Granularity and Line Edge Roughness in Advanced Multigate MOSFETs

“…Most of the FinFETs [21], [22], NW FETs [3], [6], [25], and NS FETs [26] are either directly based on experimental devices (FinFET [27], NW FET [28], NS FET [29]) or are scaled down versions of them. The FinFET used in [23] (Fig. 1(c)) is a tri-gate version of the NS FET from [29], based on current IRDS predictions [1].…”

“…TiN has two possible metal grain orientations with work-functions (φ M ) of 4.4/4.6 eV, and occurrence probabilities of 40/60%, respectively [32]. The MGG profiles are generated using Poisson-Voronoi diagrams depending on the average grain size (GS) in most of the analyzed works [3], [6], [21], [22], [23], [25], [26]. Fig.…”

A Machine Learning Approach to Modeling Intrinsic Parameter Fluctuation of Gate-All-Around Si Nanosheet MOSFETs

“…So far, the analysis of these fluctuations is accomplished by using device simulation processes [16]. Few works have been reported in the past that attempted to analyze the effects of fluctuations in GAA NS MOSFETs using device simulation [17], [18]. However, despite the high accuracy of device simulation, it is a very time-consuming process and desired alternative time-efficient methods [19].…”

Novel Modeling Approach to Analyze Threshold Voltage Variability in Short Gate-Length (15–22 nm) Nanowire FETs with Various Channel Diameters

“…However, ultrascaled SNWFETs suffer from severe threshold voltage ( V th ) variation because the device-to-device variation increases with the decrease in the effective channel width ( W eff ) and gate-length ( L G ) [ 4 , 5 ]. According to previous studies, random variations such as metal gate granularity (MGG), line edge roughness (LER), and random dopant fluctuation (RDF) cause V th variation in ultrascaled GAA transistors [ 6 , 7 , 8 , 9 , 10 ]. Additionally, the V th variation is also induced by the process variations such as junction gradient and channel thickness variation [ 11 , 12 , 13 , 14 , 15 , 16 , 17 ].…”

“…Therefore, several simulations and models have been recommended to analyze the contribution of multiple sources to V th variation. First, technology computer-aided design (TCAD) simulations are suitable for analyzing the influence of variation sources, but it is difficult to predict the cause of variation inversely from measured V th variation [ 6 , 7 , 8 , 9 , 10 ]. Second, simulation program with integrated circuit emphasis (SPICE)-based models can be applied to analyze the variation sources of measured V th variation, but it consumes time and makes an error because all devices should be calibrated [ 15 ].…”