Twisted heterostructures of two-dimensional crystals offer almost unlimited scope for the design of new metamaterials. Here we demonstrate a room temperature ferroelectric semiconductor that is assembled using mono- or few-layer MoS2. These van der Waals heterostructures feature broken inversion symmetry, which, together with the asymmetry of atomic arrangement at the interface of two 2D crystals, enables ferroelectric domains with alternating out-of-plane polarization arranged into a twist-controlled network. The last can be moved by applying out-of-plane electrical fields, as visualized in situ using channelling contrast electron microscopy. The observed interfacial charge transfer, movement of domain walls and their bending rigidity agree well with theoretical calculations. Furthermore, we demonstrate proof-of-principle field-effect transistors, where the channel resistance exhibits a pronounced hysteresis governed by pinning of ferroelectric domain walls. Our results show a potential avenue towards room temperature electronic and optoelectronic semiconductor devices with built-in ferroelectric memory functions.

The advent of two-dimensional materials has opened a plethora of opportunities in accessing ultrascaled device dimensions for future logic and memory applications. In this work, we demonstrate that a single layer of large-area chemical vapor deposition-grown molybdenum disulfide (MoS2) sandwiched between two metal electrodes can be tuned to show multilevel nonvolatile resistive memory states with resistance values separated by 5 orders of magnitude. The switching process is unipolar and thermochemically driven requiring significant Joule heating in the reset process. Temperature-dependent electrical measurements coupled with semiclassical charge transport models suggest that the transport in these devices varies significantly in the initial (pristine) state, high resistance state, and low resistance state. In the initial state, the transport is a one-step direct tunneling (at low voltage biases) and Fowler Nordeim tunneling (at higher bias) with an effective barrier height of 0.33 eV, which closely matches the Schottky barrier at the MoS2/Au interface. In the high resistive state, trap-assisted tunneling provides a reasonable fit to experimental data for a trap height of 0.82 eV. Density functional theory calculations suggest the possibility of single- and double-sulfur vacancies as the microscopic origins of these trap sites. The temperature-dependent behavior of the set and reset process are explained by invoking the probability of defect (sulfur vacancy) creation and mobility of sulfur ions. Finally, conductive atomic force microscopy measurements confirm that the multifilamentary resistive memory effects are inherent to a single-crystalline MoS2 triangle and not necessarily dependent on grain boundaries. The insights suggested in this work are envisioned to open up possibilities for ultrascaled, multistate, resistive memories for next-generation digital memory and neuromorphic applications.

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The inability to scale supply voltage and hence reduce power consumption remains a serious challenge in modern nanotransistors. This arises primarily because the Sub-threshold Swing (SS) of the thermionic MOSFET, a measure of its switching efficiency, is restricted by the Boltzmann limit (kBT/q = 60 mV/dec at 300 K). Tunneling FETs, the most promising candidates to circumvent this limit, employ band-to-band tunneling, yielding very low OFF currents and steep SS but at the expense of severely degraded ON currents. In a completely different approach, by introducing concurrent tuning of thermionic and tunneling components through metal/semiconductor Schottky junctions, we achieve an amalgamation of steep SS and high ON currents in the same device. We demonstrate sub-thermionic transport sustained up to 4 decades with SSmin ∼ 8.3 mV/dec and SSavg ∼ 37.5(25) mV/dec for 4(3) dec in few layer MoS2 dual gated FETs (planar and CMOS compatible) using tunnel injected Schottky contacts for a highly scaled drain voltage of 10 mV, the lowest for any sub-thermionic devices. Furthermore, the same devices can be tuned to operate in the thermionic regime with a field effect mobility of ∼84.3 cm2 V−1 s−1. A detailed mechanism involving the independent control of the Schottky barrier height and width through efficient device architecture and material processing elucidates the functioning of these devices. The Gate Tunable Thermionic Tunnel FET can function at a supply voltage of as low as 0.5 V, reducing power consumption dramatically.