Border traps and interface traps in HfO2/few-layer MoS2 top-gate stacks are investigated by C–V characterization. Frequency dependent C–V data shows dispersion in both the depletion and accumulation regions for the MoS2 devices. The border trap density is extracted with a distributed model, and interface traps are analyzed using the high-low frequency and multi-frequency methods. The physical origins of interface traps appear to be caused by impurities/defects in the MoS2 layers, performing as band tail states, while the border traps are associated with the dielectric, likely a consequence of the low-temperature deposition. This work provides a method of using multiple C–V measurements and analysis techniques to analyze the behavior of high-k/TMD gate stacks and deconvolute border traps from interface traps.

The electronic properties of the HfO/MoS interface were investigated using multifrequency capacitance-voltage (C-V) and current-voltage characterization of top-gated MoS metal-oxide-semiconductor field effect transistors (MOSFETs). The analysis was performed on few layer (5-10) MoS MOSFETs fabricated using photolithographic patterning with 13 and 8 nm HfO gate oxide layers formed by atomic layer deposition after in-situ UV-O surface functionalization. The impedance response of the HfO/MoS gate stack indicates the existence of specific defects at the interface, which exhibited either a frequency-dependent distortion similar to conventional Si MOSFETs with unpassivated silicon dangling bonds or a frequency dispersion over the entire voltage range corresponding to depletion of the HfO/MoS surface, consistent with interface traps distributed over a range of energy levels. The interface defects density (D) was extracted from the C-V responses by the high-low frequency and the multiple-frequency extraction methods, where a D peak value of 1.2 × 10 cm eV was extracted for a device (7-layer MoS and 13 nm HfO) exhibiting a behavior approximating to a single trap response. The MoS MOSFET with 4-layer MoS and 8 nm HfO gave D values ranging from 2 × 10 to 2 × 10 cm eV across the energy range corresponding to depletion near the HfO/MoS interface. The gate current was below 10 A/cm across the full bias sweep for both samples indicating continuous HfO films resulting from the combined UV ozone and HfO deposition process. The results demonstrated that impedance spectroscopy applied to relatively simple top-gated transistor test structures provides an approach to investigate electrically active defects at the HfO/MoS interface and should be applicable to alternative TMD materials, surface treatments, and gate oxides as an interface defect metrology tool in the development of TMD-based MOSFETs.

A high quality Al2O3 layer is developed to achieve high performance in top-gate MoS2 transistors. Compared with top-gate MoS2 field effect transistors on a SiO2 layer, the intrinsic mobility and subthreshold slope were greatly improved in high-k backside layer devices. A forming gas anneal is found to enhance device performance due to a reduction in the charge trap density of the backside dielectric. The major improvements in device performance are ascribed to the forming gas anneal and the high-k dielectric screening effect of the backside Al2O3 layer. Top-gate devices built upon these stacks exhibit a near-ideal subthreshold slope of ∼69 mV/dec and a high Y-Function extracted intrinsic carrier mobility (μo) of 145 cm2/V·s, indicating a positive influence on top-gate device performance even without any backside bias.

The benefits of O 2 plasma exposure at the contact regions of dual-gate MoS 2 transistors prior to metal deposition for high performance electron contacts are studied and evaluated. Comparisons between devices with and without the exposure demonstrate significant improvements due to the formation of a high-quality contact interface with low electron Schottky barrier (∼0.1 eV). Topographical and interfacial characterizations are used to study the contact formation on MoS 2 from the initial exfoliated surface through the photolithography process and Ti deposition. Fermi level pinning near the conduction band is shown to take place after photoresist development leaves residue on the MoS 2 surface. After O 2 plasma exposure and subsequent Ti deposition, Ti scavenges oxygen from MoO x and forms TiO x . Electrical characterization results indicate that photoresist residue and other contaminants present after development can significantly impact electrical performance. Without O 2 plasma exposure at the contacts, output characteristics of MoS 2 FETs demonstrate nonlinear, Schottky-like contact behavior compared to the linearity observed for contacts with exposure. O 2 plasma allows for the removal of the residue present at the surface of MoS 2 without the use of a high-temperature anneal. A low conduction band offset and superior carrier injection are engineered by employing the reactive metal Ti as the contact to deliberately form TiO 2 . Dual-gate MoS 2 transistors with O 2 plasma exposure at the contacts demonstrate linear output characteristics, lower contact resistance (∼20× reduction), and higher field effect mobility (∼15× increase) compared to those without the treatment. In addition, these results indicate that device fabrication process induced effects cannot be ignored during the formation of contacts on MoS 2 and other 2D materials.

Transition metal dichalcogenides (TMDs) have attracted intensive attention due to their atomic layer-by-layer structure and moderate energy bandgap. However, top-gated transistors were only reported in a limited number of research works, especially transistors with a high-k gate dielectric that are thinner than 10 nm because high-k dielectrics are difficult to deposit on the inert surface of the sulfide-based TMDs. In this work, the authors fabricated and characterized top-gated, few-layer MoS2 transistors with an 8 nm HfO2 gate dielectric. The authors show that the cleaning effect of ultrahigh vacuum annealing before high-k deposition results in significantly reduced gate leakage current of HfO2, and they show that N2 or a forming gas anneal after device fabrication affects the threshold voltage, drive current, dielectric leakage, and C-V frequency dependence. This work demonstrates how the fabrication process can affect the yield and the electrical characterization of top-gated TMD transistors, which in effect can help researchers further enhance the performance of their devices.