A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

Thoziyoor,; Ahn, Jung Ho; Monchiero,; Brockman,; Jouppi,

doi:10.1109/isca.2008.16

Cited by 173 publications

(92 citation statements)

References 30 publications

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“…We estimate area overhead of the Swarm Core microarchitecture by using CMOS circuit area models in McPAT [10] and CACTI [11]. We assume affinity value is a 32-bit fixed point value and all registers in Run Queue Buffer except for Core Affinity is 64-bit.…”

Section: Discussionmentioning

confidence: 99%

Swarm Processor System: hardware process scheduler based energy efficient multi-core system

Jeong

Kim

Lee

et al. 2014

IEICE Electron. Express

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Single-ISA heterogeneous multi-core processors can provide energy efficient performance by properly assigning workloads on two types of cores in a processor: high performance large cores and low power small cores. However, traditional process scheduling mechanism is hard to support an proper workload distribution due to an overhead of fine-grained state monitoring and scheduling. To overcome this problem, we propose Swarm Processor System which supports hardware implemented workload scheduling mechanism. In the proposed system, each core chooses a proper workload by using special hardware modules in the core instead of the scheduler of operating systems. We compare Swarm Processor System against the traditional mechanisms, and found that the proposed method shows the closest energy efficiency to the oracle case with providing stable performance.

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Section: Discussionmentioning

confidence: 99%

Swarm Processor System: hardware process scheduler based energy efficient multi-core system

Jeong

Kim

Lee

et al. 2014

IEICE Electron. Express

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“…Thus, by adding up to 64 KB of scratchpad memory, the final memory hierarchy can be very power-efficient with respect to increasing the cache memory size. Note that a configuration with 32 KB of L1 for data and another 32 KB of L1 for instructions and 64 KB for scratchpad is slightly smaller in area than a configuration with 64 KB of L1 cache [31,20], which did not result in a good energyperformance trade-off.…”

Section: Exploiting Scratchpad Memories For Active Energy Consumptionmentioning

confidence: 97%

“…Finally, after the simulation in our Jikes-DSS environment, energy figures are calculated with an updated version (v5.1) of the CACTI model [31], which is a complete energy/delay/area model, scalable to different technology nodes, for embedded SRAMs and that includes leakage as well as active power in the different components of the memory cells. For our results in this paper, we use the 90 nm technology node.…”

Section: Experimental Frameworkmentioning

confidence: 99%

Memory power optimization of Java-based embedded systems exploiting garbage collection information

Velasco

Atienza

Olcoz

2012

Journal of Systems Architecture

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a b s t r a c tNowadays, Java is used in all types of embedded devices. For these memory-constrained systems, the automatic dynamic memory manager (Garbage Collector or GC) has been always a key factor in terms of the Java Virtual Machine (JVM) performance. Moreover, in current embedded platforms, power consumption is becoming as important as performance. Thus, in this paper we present an exploration, from an energy viewpoint, of the different possibilities of memory hierarchies for high-performance embedded systems when used by state-of-the-art GCs. This is a starting point for a better understanding of the interactions between the Java applications, the memory hierarchy and the GC.Hence, we subsequently present two techniques to reduce energy consumption on Java-based embedded systems, based on exploiting GC information. The first technique uses GC execution behavior to reduce leakage energy consumption taking advantage of the low-power mode of actual multi-banked SDRAM memories and it is intended for generational collectors. This technique can achieve a reduction up to 50% of SDRAM memory leakage.The second technique involves the inclusion of a software-controlled (scratch-pad) memory that stores GC instructions under the JVM control to reduce the active energy consumption and also improve the performance of the target embedded system and it is aimed at all kind of garbage collectors. For this last technique we have experimented with two different approaches for selecting the GC code to be stored in the scratchpad memory: one static and one dynamic. Our experimental results show that the proposed dynamic scratchpad management approach for GCs enables up to 63% energy consumption reduction and 25% performance improvement during the collector phase, which means, in terms of JVM execution, a global reduction of 29% and 17% for energy and cycles, respectively.Overall, this work outlines that the key for an efficient low-power implementation of Java Virtual Machines for high-performance embedded systems is the synergy between the GC choice, the memory architecture tuning, and the inclusion of power management schemes controlled by the JVM, exploiting knowledge of the GC behavior.

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“…We base the power consumption of the DRAM on power figures provided by Micron [24] which state that a 2-channel LPDDR3 memory will consume 9.2 pJ/bit at 800 MHz. We do not use CACTI-D [25] for calculating the DRAM power as we do not require an extremely detailed power analysis.…”

Section: Power Consumption Estimationmentioning

confidence: 99%

Applying of Quality of Experience to system optimisation

Bischoff

Hansson

Al-Hashimi

2013

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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Abstract-State-of-the-art mobile devices, such as smartphones and tablets, are highly versatile and must deliver high performance across a multitude of applications. The perceived performance and resulting user experience can make or break a design. It is therefore vital that device design and optimisation take into account the expectations and perceptions of the end user, as well as the types and requirements of the applications running on the device. Traditionally, device optimisation focuses on low-level metrics, such as CPU floating point performance or GPU frame rate, rather than on the aspects most important to the end user.In this work, we investigate the applicability of Quality of Experience (QoE) to system optimisation. We define a set of measurable QoE metrics, and run a set of experiments around a web browser and two graphics benchmarks. Using the results of these experiments, we show the advantages of using QoE as an optimisation metric by demonstrating the ability to optimally trade CPU performance for energy usage whilst taking into account the user experience. We investigate two GPU benchmarks to determine the ideal number of cores for energy efficiency, whilst ensuring a sufficiently high frame rate to maintain a highquality user experience. We then look at the system as a whole, and the feasibility of using QoE to optimise performance and power consumption for the complete system, without sacrificing user experience. We achieve up to 60% savings in system energy usage with limited impact on the user experience.

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A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

Cited by 173 publications

References 30 publications

Swarm Processor System: hardware process scheduler based energy efficient multi-core system

Swarm Processor System: hardware process scheduler based energy efficient multi-core system

Memory power optimization of Java-based embedded systems exploiting garbage collection information

Applying of Quality of Experience to system optimisation

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