A comprehensive model for PMOS NBTI degradation: Recent progress

Alam, Muhammad Ashraful; Kufluoglu, H.; Varghese, D.; Mahapatra, S.

doi:10.1016/j.microrel.2006.10.012

Cited by 279 publications

(174 citation statements)

References 43 publications

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“…Indeed, different workloads Consequently, a considerable temperature difference may be exhibited by the blocks/paths in a design, which may reach 20 o C [13]. In addition, operating frequency and voltage, which do not affect stress ratio [2], are the main players in determining the power consumption, thus the thermal profile of a design. Therefore, in a DVFS design, different operating modes are characterized by different thermal profiles and, consequently, by a different BTI aging.…”

Section: B Temperature-induced Bti Variabilitymentioning

confidence: 99%

“…The dominating aging phenomenon for nanometer devices is bias temperature instability (BTI) [1], [2], whose main effect is to increase transistor threshold voltage, depending on technology parameters, operating voltage, temperature and stress ratio. If the induced performance degradation exceeds circuit time margins, it may lead to circuit failure and reduce lifetime of electronic systems.…”

Section: Introductionmentioning

confidence: 99%

“…If the induced performance degradation exceeds circuit time margins, it may lead to circuit failure and reduce lifetime of electronic systems. Great effort has been devoted to modeling of the effects of BTI and developing techniques to counteract them [2]- [6]. Design strategies adopted to tackle the negative effects of BTI aging include over-designing of the IC or monitoring the critical paths and opposing these effects during runtime [6], [7].…”

Section: Introductionmentioning

confidence: 99%

“…BACKGROUND Bias temperature instability (BTI) has been extensively modelled using a number of methods, one of which is the reaction diffusion model [2]. This allows the threshold voltage increase of a transistor to be estimated as a function of technology parameters and operating conditions.…”

Section: Introductionmentioning

confidence: 99%

“…This allows the threshold voltage increase of a transistor to be estimated as a function of technology parameters and operating conditions. Negative BTI (NBTI) is observed in pMOS transistors, and it usually dominates over the positive BTI (PBTI) observed in nMOS transistors [2], [8]. In [8], [10], an analytical model has been proposed that allows designers to estimate long term, worstcase threshold voltage shift.…”

Section: Introductionmentioning

confidence: 99%

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BTI aware thermal management for reliable DVFS designs

Chahal

Tenentes

Rossi

et al. 2016

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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Abstract-In this paper, we show that dynamic voltage and frequency scaling (DVFS) designs, together with stress-induced BTI variability, exhibit high temperature-induced BTI variability, depending on their workload and operating modes. We show that the impact of temperature-induced variability on circuit lifetime can be higher than that due to stress and exceed 50% over the value estimated considering the circuit average temperature. In order to account for these variabilities in lifetime estimation at design time, we propose a simulation framework for the BTI degradation analysis of DVFS designs accounting for workload and actual temperature profiles. A profile is generated considering statistically probable workload and thermal management constraints by means of the HotSpot tool. Using the proposed framework we explore the expected lifetime of the ethernet circuit from the IWLS05 benchmark suite, synthesized with a 32nm CMOS technology library, for various thermal management constraints. We show that margin-based design can underestimate or overestimate lifetime of DVFS designs by up to 67.8% and 61.9%, respectively. Therefore, the proposed framework allows designers to select appropriately the dynamic thermal management constraints in order to tradeoff long-term reliability (lifetime) and performance with upto 35.8% and 26.3% higher accuracy, respectively, against a temperature-variability unaware BTI analysis.

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Section: B Temperature-induced Bti Variabilitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%