A comprehensive MOSFET mismatch model

Drennan, P.G.; McAndrew, Colin C.

doi:10.1109/iedm.1999.823871

Cited by 48 publications

(28 citation statements)

References 2 publications

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“…Performance is estimated at each {s, d} combination with (13). g i,max and g i,min are the minimum and maximum values of performance g i seen so far in the optimization run.…”

Section: H Evaluation and Cost Calculationmentioning

confidence: 99%

“…The simulator was a proprietary SPICE-like simulator of a leading analog semiconductor company, with accuracy and runtime comparable to HSPICE. We used the process variation model of [13] because of its excellent accuracy, and to illustrate the ability of SANGRIA to handle a large number of process variables. Accordingly, the local variation parameters for each transistor are the following: NSUB (substrate doping concentration), VFB (flatband voltage), WINT (width variation), LINT (length variation), U0 (permittivity), RSH (sheet resistance), and TOX (gate oxide thickness).…”

Section: B Technology and Variation Modelmentioning

confidence: 99%

“…1) It must be SPICE accurate, support accurate/complex statistical models such as [13], and reflect these within its objective function. 2) It should be globally reliable-the user should not need to worry about whether the algorithm is stuck at a local optimum (and there is a difference between a nominal optimum and a statistical optimum, as Section II-B discusses).…”

Section: Introductionmentioning

confidence: 99%

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Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy

McConaghy

Gielen

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper presents SANGRIA, a tool for automated globally reliable variation-aware sizing of analog integrated circuits. Its keys to efficient search are adaptive response surface modeling, and a new concept, structural homotopy. Structural homotopy embeds homotopy-style objective function tightening into the search state's structure, not dynamics. Searches at several different levels are conducted simultaneously: The loosest level does nominal dc simulation, and tighter levels add more analyses and {process, environmental} corners. New randomly generated designs are continually fed into the lowest (cheapest) level, always trying new regions to avoid premature convergence. For further efficiency, SANGRIA adaptively constructs response surface models, from which new candidate designs are optimally chosen according to both yield optimality on model and model prediction uncertainty. The stochastic gradient boosting models support arbitrary nonlinearities, and have linear scaling with input dimension and sample size. SANGRIA uses SPICE in the loop, supports accurate/complex statistical SPICE models, and does not make assumptions about the convexity or differentiability of the objective function. SANGRIA is demonstrated on four different analog circuits having from 10 to 50 devices and up to 444 design/process/environmental variables.

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“…Performance is estimated at each {s, d} combination with (13). g i,max and g i,min are the minimum and maximum values of performance g i seen so far in the optimization run.…”

Section: H Evaluation and Cost Calculationmentioning

confidence: 99%

Section: B Technology and Variation Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy

McConaghy

Gielen

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…In [19], BSIM parameters are used for modeling. In [6], a physics based model has been proposed where mismatch is attributed to a number of physical parameters.…”

Section: Previous Workmentioning

confidence: 99%

A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs

Topaloglu

Orailoglu

2005

Proceedings. 42nd Design Automation Conference, 2005.

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Abstract-A design for test (DFT) hardware is proposed to increase the controllability of a thermometer coded current steering digital to analog converter. A procedure is introduced to reduce the diagnosis and structural test time from quadratic to linear using the proposed DFT hardware. To evaluate the applicability of the proposed technique, principal component analysis is used to create virtual process variations to simulate in lieu of semiconductor fabrication data. An architecture specific soft fault model is suggested for the diagnosis problem. Random errors according to the fault model are introduced in the virtual test environment on top of the process variations and it is shown that diagnosis of a fault is possible with high accuracy with the proposed method. The same technique employing principal component analysis is furthermore used to provide process variation-aware reference test comparison values for a structural test of the DAC. The structural test provides a mechanism to test for even unmodeled manufacturing faults. The process variation-aware test values help detect defects even under process variations. The proposed DFT hardware and method are low cost and quite suitable for a built-in self diagnosis and test implementation.

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“…Ref. [29] described a model that expresses the mismatch in terms of basic physical parameters such as the sheet resistance, channel dopant concentration, carrier mobility, and gate oxide thickness. Virtually all mismatch models for MOSFETs express the variation in the drain current as some function of random parameters, which is typically bias-dependent.…”

Section: B Mismatch In Mos Transistorsmentioning

confidence: 99%

Fast, non-Monte-Carlo estimation of transient performance variation due to device mismatch

Kim

Jones

Horowitz

2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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A comprehensive MOSFET mismatch model

Cited by 48 publications

References 2 publications

Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy

Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy

A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs

Fast, non-Monte-Carlo estimation of transient performance variation due to device mismatch

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