Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy

Abstract

Abstract-This paper presents SANGRIA, a tool for automated globally reliable variation-aware sizing of analog integrated circuits. Its keys to efficient search are adaptive response surface modeling, and a new concept, structural homotopy. Structural homotopy embeds homotopy-style objective function tightening into the search state's structure, not dynamics. Searches at several different levels are conducted simultaneously: The loosest level does nominal dc simulation, and tighter levels add more analyses and {process, environmental} corners. New randomly generated designs are continually fed into the lowest (cheapest) level, always trying new regions to avoid premature convergence. For further efficiency, SANGRIA adaptively constructs response surface models, from which new candidate designs are optimally chosen according to both yield optimality on model and model prediction uncertainty. The stochastic gradient boosting models support arbitrary nonlinearities, and have linear scaling with input dimension and sample size. SANGRIA uses SPICE in the loop, supports accurate/complex statistical SPICE models, and does not make assumptions about the convexity or differentiability of the objective function. SANGRIA is demonstrated on four different analog circuits having from 10 to 50 devices and up to 444 design/process/environmental variables.

Open-ended evolution to discover analogue circuits for beyond conventional applications

“…Open-ended methods of evolutionary analogue circuit synthesis have been challenged with an important question [13], ''Are such methods able to create solutions that, when realized in silicon, are valid and trustworthy enough?'' In [14], the set of experiments have proven that the open-ended techniques enable the design of low/high-pass filters with topology-based robustness.…”

“…The other approach proposes, at the outset, an evolutionary system targeted at producing robust designs [13,14,17]. In the current study, we adopt the first approach focusing on the exploration of the technique's capabilities to create novel designs, leaving the evolution of robustness for the next stage.…”

“…Therefore, in this paper, we decided to target much more complex analogue circuits, some of which have never been designed before. The choice of targets for the synthesis is based on the openended nature of our technique because we assume that the methods with constraints [28][29][30][31][32] and with pre-specified substructures [13,26,30,31,33,34] are likely to be limited and after synthesis result only in conventional applications of analog circuits.…”

Exploring a homotopy approach for the design of nanometer digital circuits tolerant to process variations

“…The use of CAD tools to design optimization of the overall circuit delay has been proposed in the literature [7,8,9]. Most common methodologies used to design circuits tolerant to process variations are the gate-sizing optimization algorithms [7,8,9], custom design [5,10,11], parallel-gates [10,12] and specialized libraries [13].…”

Fast Time-Domain Simulation for Reliable Fault Detection

“…A refinement here is the use of a response surface model technique [21], which can reduce the cpu costs of evaluating many Monte Carlo samples. A new class in this area is provided by recent techniques from Polynomial Chaos Expansions (PCEs), where the expansions effectively provide a response surface facility [14], [29].…”