A Comprehensive Study of a Single-Transistor Latch in Vertical Pillar-Type FETs With Asymmetric Source and Drain

Lee, Seung-Wook; Kim, Seongyeon; Hwang, Kyu‐Man; Jin, Ik Kyeong; Hur, Jae; Kim, Dohyun; Son, Jun Woo; Kim, Wu‐Kang; Choi, Yang‐Kyu

doi:10.1109/ted.2018.2869670

Cited by 10 publications

(5 citation statements)

References 15 publications

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“…The shell gate length ( L g ) and the Si channel thickness ( T Si ) were fixed to 500 nm and 200 nm, respectively. In vertical Si NW structure, an asymmetric doping concentration is unavoidable due to the different ion implantation energies for the top drain and bottom source regions [ 23 ]. Therefore, the doping concentrations of channel, source, and drain were modeled to 1 × 10 17 cm −3 , 5 × 10 19 cm −3 , and 1 × 10 20 cm −3 , respectively.…”

Section: Device Structure and Simulation Methodologymentioning

confidence: 99%

A Vertical Single Transistor Neuron with Core–Shell Dual-Gate for Excitatory–Inhibitory Function and Tunable Firing Threshold Voltage

Lee

Jeon²,

Kim³

2022

Micromachines

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A novel inhibitable and firing threshold voltage tunable vertical nanowire (NW) single transistor neuron device with core–shell dual-gate (CSDG) was realized and verified by TCAD simulation. The CSDG NW neuron is enclosed by an independently accessed shell gate and core gate to serve an excitatory–inhibitory transition and a firing threshold voltage adjustment, respectively. By utilizing the shell gate, the firing of specific neuron can be inhibited for winner-takes-all learning. It was confirmed that the independently accessed core gate can be used for adjustment of the firing threshold voltage to compensate random conductance variation before the learning and to fix inference error caused by unwanted synapse conductance change after the learning. This threshold voltage tuning can also be utilized for homeostatic function during the learning process. Furthermore, a myelination function which controls the transmission rate was obtained based on the inherent asymmetry between the source and drain in vertical NW structure. Finally, using the CSDG NW neuron device, a letter recognition test was conducted by SPICE simulation for a system-level validation. This multi-functional neuron device can contribute to construct a high-density monolithic SNN hardware combining with the previously developed vertical synapse MOSFET devices.

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Section: Device Structure and Simulation Methodologymentioning

confidence: 99%

A Vertical Single Transistor Neuron with Core–Shell Dual-Gate for Excitatory–Inhibitory Function and Tunable Firing Threshold Voltage

Lee

Jeon²,

Kim³

2022

Micromachines

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“…The fabrication of VP‐FeFET can be proceeded by connecting the MFM capacitor to the vertical‐pillar‐type transistor using the BEOL process. [ 29,30 ] MFMIS is the equivalent gate stack of the VP‐FeFET, implying that the capacitance ratio between the ferroelectric film and gate insulator can be modulated by adjusting channel height without increasing the lateral footprint of the device.…”

Section: Concept Of Device and Model Calibrationmentioning

confidence: 99%

Vertical‐Pillar Ferroelectric Field‐Effect‐Transistor Memory

Lee

Kim

et al. 2021

Physica Rapid Research Ltrs

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In recent years, following trends in developing semiconductors, extensive research has been conducted to develop a hafnia‐based ferroelectric field effect transistor (FeFET) memory. However, its fundamental endurance limitation, which stems from early degradation of the gate insulator, has been a major obstacle to the development of FeFETs, with no clear solution despite attempting various approaches to high‐speed and high‐reliability FeFETs. Herein, a novel metal–ferroelectric–metal–insulator–semiconductor FeFET with vertical‐pillar channel and metal–ferroelectric–metal capacitor (VP‐FeFET) that can adjust the capacitance ratio between the ferroelectric film and gate insulator by modulating the channel height is proposed. The optimized VP‐FeFET exhibits a significantly reduced electric field (≤1.5 MV cm−1) through the gate insulator, resulting in a substantially enhanced FeFET endurance. Furthermore, the proposed FeFET achieved a large memory window of ≈5 V and a high program/erase speed of ≈100 ns. These merits are achieved without increasing the footprint of the FeFET device. This approach to high‐performance FeFET can be applied extensively to next‐generation nonvolatile memory devices.

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“…Various merits of the vertical channel can be observed, such as a higher cell area efficiency, stronger robustness against SCEs, and a larger degree of freedom in determining the channel length. [20][21][22][23][24][25][26][27] Different types of multiple-gate MOSFETs have been reported, 1,28,29) and the vertical-channel structure is actually found in one of these cases. Compared with the other types, the vertical-channel MOSFET has the smallest footprint and the most ideal current-voltage characteristics.…”

Section: Introductionmentioning

confidence: 99%

Analysis on performances of ultra-thin vertical MOSFET depending on position of gate–drain misalignment

Kim,

Cho

2024

Jpn. J. Appl. Phys.

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In this work, a series of technology computer-aided design (TCAD) device simulations have been carried out to investigate the effects of gate underlap and overlap structures on device performances of vertical-channel MOSFET. The device characterizations were conducted in both aspects of DC and high-frequency operations for higher completeness of this work since both are not usually optimized at the same time under the same structural and processing conditions. Under the underlap condition, slight degradation in the on-state current Ion drivability was observed. A noticeable off-state current Ioff increases were witnessed under the underlap conduction. It is explicitly demonstrated that excessive gate underlap results in non-ideal effects including degradation of subthreshold swing (S), worsening of drain-induced barrier lowering (DIBL), lowering of maximum transconductance (gm,Max). Although fT and fmax were sustained to be high under overlap and gate-drain alignment conditions,

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A Comprehensive Study of a Single-Transistor Latch in Vertical Pillar-Type FETs With Asymmetric Source and Drain

Cited by 10 publications

References 15 publications

A Vertical Single Transistor Neuron with Core–Shell Dual-Gate for Excitatory–Inhibitory Function and Tunable Firing Threshold Voltage

A Vertical Single Transistor Neuron with Core–Shell Dual-Gate for Excitatory–Inhibitory Function and Tunable Firing Threshold Voltage

Vertical‐Pillar Ferroelectric Field‐Effect‐Transistor Memory

Analysis on performances of ultra-thin vertical MOSFET depending on position of gate–drain misalignment

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