Owing to their high scalability and superior complementary metal–oxide–semiconductor (CMOS) compatibility, HfO2‐based ferroelectric field‐effect transistors (FeFETs) are proved to be promising candidates for emerging nonvolatile memory devices. However, the poor endurance of these FeFETs, which is attributed to the degradation of the interfacial dielectric layer, is a serious obstacle for commercialization. In FeFETs with a metal–ferroelectric–insulator–semiconductor gate stack, the strong electric field across the interfacial dielectric layer mainly induces charge injection/trapping and limits endurance to <106 cycles. Herein, optimum condition of switching polarization (Pnormals) of ferroelectric materials and a new structural approach to reduce the strength of the electric field across the interfacial dielectric layer and improve memory window (MW) and reliability properties are presented. Based on numerical simulation, it is found that an interfacial electric field increases with Pnormals, and a metal–ferroelectric–metal–insulator–semiconductor FeFET with a 3D channel structure is effective to have high ratio of dielectric capacitance to ferroelectric capacitance, resulting in low electric field through the interfacial layer and large MW.

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The ferroelectric field effect transistor (FeFET) has significant potential as the leading contenders to replace current NAND flash memory due to its high operation speed and low power consumption along...

We present herewith a novel approach of equally thick AFE/FE (ZrO2/HZO) bilayer stack heterostructure films for achieving an equivalent oxide thickness (EOT) of 4.1 Å with a dielectric constant (κ) of 56 in complementary metal-oxide semiconductor (CMOS) compatible metal–ferroelectric–metal (MFM) capacitors using a high-pressure annealing (HPA) technique. The low EOT and high κ values were achieved by careful optimization of AFE/FE film thicknesses and HPA conditions near the morphotropic phase boundary (MPB) after field cycling effects. Stable leakage current density (J < 10–7 A/cm2 at ±0.8 V) was found at 3/3 nm bilayer stack films (κ = 56 and EOT = 4.1 Å) measured at room temperature. In comparison with previous work, our remarkable achievement stems from the interfacial coupling between FE and AFE films as well as a high-quality crystalline structure formed by HPA. Kinetically stabilized hafnia films result in a small grain size in bilayer films, leading to reducing the leakage current density. Further, a higher κ value of 59 and lower EOT of 3.4 Å were found at 333 K. However, stable leakage current density was found at 273 K with a high κ value of 53 and EOT of 3.85 Å with J < 10–7 A/cm2. This is the lowest recorded EOT employing hafnia and TiN electrodes that are compatible with CMOS, and it has important implications for future dynamic random access memory (DRAM) technology.

Flash memory is a promising candidate for use in in‐memory computing (IMC) owing to its multistate operations, high on/off ratio, non‐volatility, and the maturity of device technologies. However, its high operation voltage, slow operation speed, and string array structure severely degrade the energy efficiency of IMC. To address these challenges, a novel negative capacitance‐flash (NC‐flash) memory‐based IMC architecture is proposed. To stabilize and utilize the negative capacitance (NC) effect, a HfO2‐based reversible single‐domain ferroelectric (RSFE) layer is developed by coupling the flexoelectric and surface effects, which generates a large internal field and surface polarization pinning. Furthermore, NC‐flash memory is demonstrated for the first time by introducing a RSFE and dielectric heterostructure layer in which the NC effect is stabilized as a blocking layer. Consequently, an energy‐efficient and high‐throughput IMC is successfully demonstrated using an AND flash‐like cell arrangement and source‐follower/charge‐sharing vector‐matrix multiplication operation on a high‐performance NC‐flash memory.