High‐Performance and High‐Endurance HfO₂‐Based Ferroelectric Field‐Effect Transistor Memory with a Spherical Recess Channel

Abstract

Owing to their high scalability and superior complementary metal–oxide–semiconductor (CMOS) compatibility, HfO2‐based ferroelectric field‐effect transistors (FeFETs) are proved to be promising candidates for emerging nonvolatile memory devices. However, the poor endurance of these FeFETs, which is attributed to the degradation of the interfacial dielectric layer, is a serious obstacle for commercialization. In FeFETs with a metal–ferroelectric–insulator–semiconductor gate stack, the strong electric field across the interfacial dielectric layer mainly induces charge injection/trapping and limits endurance to <106 cycles. Herein, optimum condition of switching polarization (Pnormals) of ferroelectric materials and a new structural approach to reduce the strength of the electric field across the interfacial dielectric layer and improve memory window (MW) and reliability properties are presented. Based on numerical simulation, it is found that an interfacial electric field increases with Pnormals, and a metal–ferroelectric–metal–insulator–semiconductor FeFET with a 3D channel structure is effective to have high ratio of dielectric capacitance to ferroelectric capacitance, resulting in low electric field through the interfacial layer and large MW.

Neuromorphic devices based on fluorite‐structured ferroelectrics

“…(E) Reproduced with permission from Lee et al, JEDS.2021.3056438 (2021) under Creative Commons Attribution license (CC BY 4.0) 210 . (F) Reproduced with permission 211 . Copyright 2021, John Wiley and Sons.…”

“…There have been many attempts to change the channel geometry of FeFETs to overcome the size‐dependent challenge for developing analog synapses with FeFETs, as shown in Figure 5D–F 172,210,211 . Figure 5D shows the first demonstration of a (Hf,Zr)O 2 ‐based junctionless FinFET 172 .…”

Novel Approach to High κ (∼59) and Low EOT (∼3.8 Å) near the Morphotrophic Phase Boundary with AFE/FE (ZrO2/HZO) Bilayer Heterostructures and High-Pressure Annealing

“…Like other nanoelectronics, logic and memory technologies have been advanced by employing unique materials, a new device structure, and an advanced process. − In this view, ferroelectric (FE) devices of hafnium zirconium oxide (HZO) have gained much popularity in recent years due to their ability to achieve satisfactory leakage current density and a lower EOT as well as their excellent CMOS compatibility with TiN electrodes. ,− Additionally, ferroelectric hafnia films are greatly preferred in memory technology due to their availability of the mature ALD deposition technique, suitability for 3D structures, and large band gap (∼5.6 eV). − Potential applications of HZO include ferroelectric field effect transistors (FeFETs), ferroelectric random access memory (FeRAM), negative capacitance FETs (NCFETs), synaptic and logic devices, energy storage supercapacitors, piezoelectric sensors, and energy harvesters. ,− In view of the above advantages, the hafnia material system can be a promising candidate for achieving high-κ, reducing EOT and leakage current.…”

Fabrication Strategies of Metal–Ferroelectric–Insulator–Silicon Gate Stacks Using Ferroelectric Hf–Zr–O and High-k HfO2 Insulator Layers for Securing Robust Ferroelectric Memory Characteristics

“…For the device applications of FeFETs employing HfO 2 -based ferroelectric gate insulator (GI), it is essential to design the gate stack structures so as to fully exploit the saturated ferroelectric polarization and to obtain robust device operations in terms of efficient voltage distribution across the gate stack. From this point of view, the metal–ferroelectric–metal–insulator–semiconductor (MFMIS) gate stack structures have been explored for realizing the robust NVM characteristics, in which the areas of MFM and MIS capacitors can be independently prepared by inserting an intermediate metal layer between the ferroelectric and insulator layers (ILs). − For the conventional metal–ferroelectric–insulator–semiconductor (MFIS) structures using SiO 2 as the IL, the maximum available charge capacity ( Q max ), which is defined as the product of dielectric permittivity and dielectric breakdown field, stored in the SiO 2 IL is subject to be lower than the remnant polarization ( P r ) of the ferroelectric layer (FL), as the area ratio of MIS capacitor to MFM capacitor ( A MIS / A MFM ) is fixed as 1. − As a result, it is difficult to use the fully saturated polarization–electric field ( P – E ) hysteresis loop due to the breakdown of the SiO 2 IL. , On the contrary, for the MFMIS gate stack, the area of the MFM capacitor can be reduced by increasing A MIS / A MFM ; hence, the mismatch of the available capacitance between two capacitors can be solved by equivalently decreasing the P r value of FL . In other words, the use of saturated polarization curves enhances the immunity against the depolarization field during the retention period.…”