A Comprehensive Survey on Distinctive Implementations of Carry Select Adder

Umapathi, N.; Krishna, G. Vamsi; Srinivas, L.

doi:10.1109/icnte51185.2021.9487718

Cited by 5 publications

(1 citation statement)

References 6 publications

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“…The research in this is in the works. The recently suggested complete sum multiplier [2][3][4][5][6][7][8][9][10][11][12] was reversible circuits for various applications. In these reversible designs, the Multiplier circuits are most important as they are the key circuits in designing of computer systems such as ALU and mobile phones such as image and sound processing applications.…”

Section: Introductionmentioning

confidence: 99%

Design of Fault Tolerant Array Multiplier Using Parity Preserving Reversible Gate

-¹

2023

IJFMR

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The digital designs with Reversible logic are more popular now days because of the increased demand of low power usage. Some of the Reversible logic gates are discussed in this paper. This paper also introduces a Parity Preserving Reversible Gate (PPRG) which is used in the fault tolerant devices design such as adders, subtractors and multipliers. The design of an array multiplier by using fault tolerant parallel adders is discussed in this paper. The fault tolerant parallel adders are designed using fault tolerant full adders and half adders and these adders are designed through Parity Preserving Reversible Gate. These adders and multipliers are useful in designing complex circuits such as ALU.

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