No abstract

Here in this paper we discuss about an efficient method k-means clustering for detection of tumour volume in brain MRI scans. This paper describes an efficient method for automatic brain tumor segmentation for the extraction of tumour tissues from MR images. It combines Perona and Malik anisotropic diffusion model for image enhancement and K means clustering techniques for grouping tissues belonging to a specific group. The developments in the application of informa technology have completely changed the world. The obvious reason for the introduction of computer system is: reliability, accuracy, simplicity and ease of use. Besides, the customization and optimization features of a computer system and among the oth major driving forces in adopting and subsequently strengthening the computer aided systems. On medical imaging, an image is captured, digitized and processed fordoing segmentation and for extracting important information. Manual segmentation is an alternate method for segmenting an image. This method is not only tedious and time consuming, but also produces inaccurate results. Therefore, there is a strong need to have some efficient computer based system that accurately defines the boundaries of brain tissues along with minimizing the chances of user interaction with the system.

Template matching is a diagnostic approach for detecting a patch of a template image in a given source image. This plays a vital role in multitudinal computer vision applications. In this paper, we propose a methodology that makes the naive template matching algorithm scale and angle invariant during the image recognition process where the source and template is converted to gray scale which makes the technique enhance its proficiency. The proposed algorithm handles the arbitrary modulations of the image patch with respect to size and angle by an exhaustive search of all combinations of sizes are done along with populous combinations of angles. The images adapted are subjected to certain filtering and convolution methods which deepens the quality of the images which in turn assists in retrieving the features with accuracy. The image intensities are adjusted using histogram equalization to enhance the image contrast. These images are then subjected to perform template matching using normalized cross correlation to measure similarity between those two images.

Multi-pattern matching is known to require intensive memory accesses and is often a performance bottleneck. Hence specialized hardware-accelerated algorithms are being developed for line-speed packet processing. While several pattern matching algorithms have already been developed for such applications, we find that most of them suffer from scalability issues. We present a hardware-implementable pattern matching algorithm for content filtering applications, which is scalable in terms of speed, the number of patterns and the pattern length. We modify the classic Aho-Corasick algorithm to consider multiple characters at a time for higher throughput. Furthermore, we suppress a large fraction of memory accesses by using Bloom filters implemented with a small amount of on-chip memory. The resulting algorithm can support matching of several thousands of patterns at more than 10 Gbps with the help of a less than 50 KBytes of embedded memory and a few megabytes of external SRAM.

Intellectual property takes several forms, the most important of which are patents, copyrights, and trade rights. Patents protect inventions. One can patent methods and processes, new varieties of plants, and (more weakly) designs. The VSI alliance proposed the usage of the three approaches for proper protection of IP designs. The detection approach directly interacts with the VLSI design, and is considered an overhead on the design cycle. IP watermarking and IP fingerprinting are the main approaches used, where the design is watermarked (tagged) then different tracking techniques are used to keep track of the usages of such design. Reuse-Based design methodology has taken hold, the very large scale integration (VLSI) design industry is confronted with the increasing threat of intellectual property (IP) infringement.