A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability

Jia, Rui; Yang, Haigang; Lin, Colin Yu; Chen, Rui; Wang, Xingang; Guo, Zhenhong

doi:10.1109/tcad.2015.2504922

Cited by 18 publications

(6 citation statements)

References 34 publications

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“…Table 2 shows the implementation of different Xilinx FPGA devices for existing and LC-R4-RFIR methods, which used for analyzing the performance parameters like LUTs, the number of flip-flops, slices, Input Output Block (IOB) and operating frequency for Virtex-6, Virtex-6LP, Virtex-7. In existing method [7] [8], shifter and adder has been used to perform the multiplication operation. That method requires more area and computation time, and hardware utilization.…”

Section: Frequencymentioning

confidence: 99%

“…That filter architecture design achieved a low-area and power consumption. But drawback of this technique is not discussing the dynamically reconfigurable mechanism [8]. The pipelined modified booth multiplier technique employed for RFIR filter architecture, which is the order of the filter to improve low-power consumption than existing architectures, but this strategy is not possible for the more-power applications [9,10].…”

Section: Introductionmentioning

confidence: 99%

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Low Cost FPGA Implementation of RFIR Filter Based on a Radix-4 Algorithm

Venkateswarlu¹,

Kumar²

2018

IJIES

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The Reconfigurable Finite Impulse Response (RFIR) filter design is a significant operation in Digital Signal Processing (DSP). The RFIR designs often implemented to evaluate the system performance and hardware utilization. The traditional RFIR filter design depends on more sub module such as subtractions, adders, and shifters, which occupies more area and increase the system complexity. To overcome this problem, a Low Cost-Radix4-RFIR (LC-R4-RFIR) filter design is introduced. This research work designed an efficient RFIR filter with the help of Radix 4 approach, which reduced the filter area and hardware utilization. The RFIR filter was designed by using R4 approach for multiplication operation. Multiplication is the one of the main process of adding a number of Partial Products (PPs) Hence, integer multiplication is implemented in serial parallel mode by employing an accumulator to add these PPs. Using R4, the multiplication operation performed which mitigated the area and hardware utilization of the RFIR design. In Field Programmable Gate Array (FPGA) implementation, the number of Look Up Table (LUT), Slice, flip-flop, area, and frequency calculated for different Virtex devices such as Virtex-6, Virtex-6 Low Power (LP) and Virtex-7. This FPGA experimental results showed that the LC-R4-RFIR filter design performed better compared to conventional FIR filter designs.

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Section: Frequencymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low Cost FPGA Implementation of RFIR Filter Based on a Radix-4 Algorithm

Venkateswarlu¹,

Kumar²

2018

IJIES

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“…Wang, and Z.H. Guo [5] introduced novel RFIR filter design based on statistics centric reconfigurable (SCR) FIR filter architecture. The experimental results were analyzed by considering performance parameters such as area, speed, and power for the high-order FIR filters and they have concluded that proposed RFIR filters have improvements in their performance over the conventional FIR filter but did not discuss about the dynamically reconfigurable mechanism.…”

Section: Literature Surveymentioning

confidence: 99%

FPGA Implementation of Reconfigurable FIR Filter using Carry Bypass Adder

Rizwan¹,

Rasool²

2018

International Journal of Advanced Research in Computer and Comm

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Software-Defined Radio (SDR) is a radio communication system where components that have been traditionally implemented in hardware (e.g. mixers, filters, amplifiers, modulators/demodulators, detectors, etc.) are instead implemented by means of software on a personal computer or embedded system. Reconfigurable Finite Impulse Response (RFIR) filter plays an important role in SDR systems, whose filter co-efficient change dynamically during runtime. In this paper, Low Cost Carry Bypass adder Reconfigurable Finite Impulse Response (LC-CBA-RFIR) is introduced to perform the RFIR filter operations. DRAM-based Reconfigurable Partial Product Generators (DRPPG) consists of MUX and dual port distributed RAM, which has co-efficient to perform a FIR filter operation. With the help of Verilog code, the RFIR filter architecture was verified in Modelsim software. The same Verilog code was used to analyse the FPGA performances such as LUT, flip flop, slice and frequency. After implementing FPGA, all the performance improved in LC-CBA-RFIR method compared to the conventional methods.

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“…[2, 5-8, 15, 23, 24, 26, 33]. In particular, the RFIR filters are often applied in scenarios where low power utilization, lesser chip area and self-adjustment at higher speeds are required [5,8,15,26,33].…”

Section: Introductionmentioning

confidence: 99%

An Efficient Block-Based Architecture for Reconfigurable FIR Filter Using Partial-Product Method

Shrivastava

Kumar

Tiwari

et al. 2021

Circuits Syst Signal Process

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Multipliers are the most demanding component of any filter. They not only dominate most of the chip area but also contribute to most of the computational delay. An efficient realization of filter thus requires optimization of the multipliers. In this paper, a high performance block reconfigurable finite impulse response filter structure is presented. Block-based realization improves the overall throughput of the structure. A novel partial-product-based structure is proposed for Multiply and Accumulation operation, instead of traditional multipliers-based structure. Pipelining and parallelism in the structure improves the throughput of the design. The reuse of the partial products reduces the number of adders and increases the speed, thereby reducing the area-delay product (ADP) and energy-per output (EPO), in comparison with the earlier reported structures. The comparative analysis is done with the help of ASIC synthesis results and the results show that the proposed architecture for filter order 16 and block input 8requires 28.91% less ADP and 25.72% less EPO than the earlier reported architecture.

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A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability

Cited by 18 publications

References 34 publications

Low Cost FPGA Implementation of RFIR Filter Based on a Radix-4 Algorithm

Low Cost FPGA Implementation of RFIR Filter Based on a Radix-4 Algorithm

FPGA Implementation of Reconfigurable FIR Filter using Carry Bypass Adder

An Efficient Block-Based Architecture for Reconfigurable FIR Filter Using Partial-Product Method

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