A computationally efficient technique for real-time detection of particular-slope edges

Mabrouk, Ahmed; Hassim, Norhidayah; Elshafiey, Ibrahim

doi:10.1007/s11554-013-0346-1

Cited by 2 publications

(1 citation statement)

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“…2D-convolution is an important concept in several areas of math and engineering including computer vision, digital image processing for medical applications, statistics applications, object recognition and so on [3,7,8,10,15,17,24,29,14,11,12,34,1,4]. Convolution operates on two signals in 1D filtering operation or two images in 2D filtering operation.…”

Section: Spatial-domain Convolution Filtersmentioning

confidence: 99%

An FPGA 2D-convolution unit based on the CAPH language

Aguilar-González

Arias-Estrada

Pérez-Patricio

et al. 2015

J Real-Time Image Proc

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International audienceConvolution is an important operation in image processing applications, such as edge detection, sharpening , adding blurring and so on. Convolving video streams in real-time is a challenging task for PC systems, however, FPGA devices can successfully be used in these tasks. In this article, the design and implementation of a reconfigurable FPGA architecture for 2D-convolution filtering is described. The filtered frames are calculated at a rate of 103 frames per second for images up to 1200×720 pixel resolution. By using a shift-based arithmetic and circular buffers, the developed FPGA architecture allows to reduce the hardware resources consumption up to 98% compared to the conventional convolution implementations , provides high speed processing and enables to manage large number of different convolution kernels. On the other hand, by using the CAPH language it is possible to reduce the design time up to 75% compared to the plain VHDL design. Furthermore, to maintain high flexibility in concordance with the input video, the developed hardware allows to configure the resolution of the input images with values of 3 × Y up to 1200 × Y , and allows scalability for different sizes of convolution kernels of simple and systematic form. Finally , the developed FPGA architecture for the proposed method was implemented and validated in an FPGA Cyclone II EP2C35F672C6 embedded in an Altera development board DE2

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