A computer architecture laboratory course using programmable logic

Brown, Geoffrey; Vrana, N. M.

doi:10.1109/13.387212

Cited by 19 publications

(11 citation statements)

References 24 publications

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“…Traditionally, the principles of pipelined and superscalar execution have been taught by using trace-driven simulation [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][71][72][73][74] , or FPGA-based hardware emulation 21,[30][31][32][33][34] . Surveys of simulation resources are presented by Wolffe et al 75,77 , and Yehezkel et al 76 However, simulator bugs and modeling inaccuracies can lead to significant errors in performance measurements [78][79][80][81][82][83][84] , and so may result in wrong design decisions.…”

Section: Related Workmentioning

confidence: 99%

“…Traditionally, the principles of pipelined and superscalar execution have been taught with three approaches: 1) trace-driven simulation with existing tools [6][7][8][9][10][11][12][13][14][15][16][17][18] ; or 2) implementation of a trace-driven simulator by using a programming language such as C, often by filling only missing sections in skeleton code provided by the instructors [19][20][21] ; or 3) implementation of a processor using a commercial hardware description language (HDL), such as Verilog 22 or VHDL [23][24] as reported by several authors [25][26][27][28] , or an academic HDL 20,29 , and then simulating it with existing tools or with an FPGA-based hardware emulation system 21,[30][31][32][33][34] . In the second and third approaches, the implementations are verified with test sequences provided by the instructors, and possibly with additional test sequences defined by students.…”

Section: Introductionmentioning

confidence: 99%

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Integrating Formal Verification into an Advanced Computer Architecture Course

Velev

2005

IEEE Trans. Educ.

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Abstract. The paper presents a sequence of three projects on design and formal verification of pipelined and superscalar processors. The projects were integrated-by means of lectures and preparatory homework exercises-into an existing advanced computer architecture course taught to both undergraduate and graduate students in a way that required them to have no prior knowledge of formal methods. The first project was on design and formal verification of a 5-stage pipelined DLX processor, implementing the six basic instruction types-register-register-ALU, registerimmediate-ALU, store, load, jump, and branch. The second project was on extending the processor from project one with ALU exceptions, a return-from-exception instruction, and branch prediction; each of the resulting models was formally verified. The third project was on design and formal verification of a dual-issue superscalar version of the DLX from project one. The preparatory homework problems included an exercise on design and formal verification of a staggered ALU, pipelined in the style of the integer ALUs in the Intel Pentium 4. The processors were described in the high-level hardware description language AbsHDL that allows the students to ignore the bit widths of word-level values and the internal implementations of functional units and memories, while focusing entirely on the logic that controls the pipelined or superscalar execution. The formal verification tool flow included the term-level symbolic simulator TLSim, the decision procedure EVC, and an efficient SAT-checker; this tool flow-combined with the same abstraction techniques for defining processors with exceptions and branch prediction, as used in the projects-was applied at Motorola to formally verify a model of the M•CORE processor, and detected bugs. The course went through two iterations-offered at the Georgia Institute of Technology in the summer and fall of 2002-and was taught to 67 students, 25 of whom were undergraduates.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Integrating Formal Verification into an Advanced Computer Architecture Course

Velev

2005

IEEE Trans. Educ.

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“…While faculty at various schools have devised many excellent tools to study computer architecture 5 -many of which provide much in the understanding of an existing architecture-they do not give students a lot of freedom in design, trade-offs, and real systems. Also, many schools construct their own in-house EDA tools 6 instead of using industrial applications. This keeps the design tools simple and 49 MAY-JUNE 2000…”

Section: Related Curriculamentioning

confidence: 99%

Building real computer systems

Uht

Lo²,

Ying³

et al. 2000

IEEE Micro

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“…However, the teaching depth of these courses materials is varied from one university to the other. While some universities are focused on the theoretical concepts of processor design, other universities cover all the key elements required for teaching processor design that are mentioned in the previous section [5]- [8].…”

Section: Previous Workmentioning

confidence: 99%

A Processor Design Course Project: Creating Soft-Core MIPS Processor Using Step-by-Step Components’ Integration Approach

Elkateeb¹

2011

IJIET

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Abstract-Design and implementation of a soft-core MIPS processor using field-programmable gate array (FPGA) technology will be addressed in this paper. Teaching processor architecture and design is considered the key element of the student learning in the undergraduate Computer Engineering program; as such, this project was developed to enrich students' experience in this field. This paper presents a practical introduction to soft-core processor design through the use of step-by-step integrating of the processor's components. Students implemented their processors using Xilinx ISE design tools and downloaded their designs to Xilinx ML 501 FPGA boards, which used Xilinx Virtex 5 chips. A designed and developed soft-core processor provided students with a starting point for applying their designed processors in follow-up courses such as Embedded Systems and Senior Design Project. Students' assessment of the soft-core processor design was analyzed, which indicated that they are confident in confronting the next step of constructing advanced processor architecture.Index Terms-MIPS processor, field-programmable gate array (FPGA), Xilinx design tools, VHDL.

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A computer architecture laboratory course using programmable logic

Cited by 19 publications

References 24 publications

Integrating Formal Verification into an Advanced Computer Architecture Course

Integrating Formal Verification into an Advanced Computer Architecture Course

Building real computer systems

A Processor Design Course Project: Creating Soft-Core MIPS Processor Using Step-by-Step Components’ Integration Approach

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