With the transition to ≤28-nm CMOS technology nodes, the surface analytical challenges with regard to steadily decreasing dimensions and still growing materials options raise the demand of high performing surface analysis techniques. Characterization of ultrathin films and multilayer stacks, especially in high-k metal gate stacks, by means of low energy ion scattering spectroscopy (LEIS) with its monolayer sensitivity has been established as a very useful analysis technique next to Auger electron spectroscopy, X-ray photoelectron spectroscopy, and time-of-flight secondary ion mass spectrometry. Questions regarding film nucleation, growth, coverage, and diffusion can be answered, thereby enabling those processes to be controlled appropriately.In this work, growth studies of ALD HfO 2 and TiN are shown, as well as film thickness determination based on surface spectra. PVD aluminum and lanthanum, acting as work function metals on the gate oxide, were deposited, and their film formation and closure were investigated.Further application fields of LEIS have emerged from the characterization of in-die features on patterned wafers. As presented on test arrays, it is possible to detect material deep in trenches. This is an advantage if residues need to be identified after etch or clean processes. KEYWORDS ALD, growth study, high-k metal gate, LEIS, PVD, work function metal 1 | INTRODUCTION CMOS technology progression beyond the 32-nm node requires the implementation of new materials such as high-k gate dielectrics and ultra thin metal gates. The scaling of conventional Poly SiON transistor structures is limited because of too high gate leakage currents. For 32nm CMOS and beyond, the needed short channel properties can only be reached by high-k metal gate (HKMG) technology. There are 2 integration approaches in implementing HKMG into CMOS: Gate First andGate Last. In the Gate First integration, as the name implies, the HKMG is formed first, followed by gate patterning, source/drain (S/D) and contact formation. In the Gate Last integration, a dummy gate is created, followed by gate patterning and S/D formation. The dummy gate is then removed, and the HKMG and finally the contacts are manufactured 1-6 ( Figures 1 and 2). The operation of these very complex integration schemes requires comprehensive studies, in order to define the materials and material combinations with the appropriate properties and compatibility, and the optimum work function tuning metals. Deposition processes, as well as cleaning and etching strategies, have to be developed or adapted. The properties of the ultra thin films in a HKMG stack strongly influence the transistor performance. Consequently, the introduction of atomic layer deposition (ALD) processes, replacing the established chemical, metal organic, and physical vapour deposition processes (CVD, MO-CVD, PVD), became a requirement. Key questions for the analyst are about nucleation, film growth, or diffusion. The transient regime in film formation of high-k gate oxide, metal gate, and the work f...
