Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05 2005
DOI: 10.1145/1120725.1120870
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A configurable AES processor for enhanced security

Abstract: We propose a configurable AES processor for extended-security communication. The proposed architecture can provide up to ¾ ½ different AES block cipher schemes within a reasonable hardware cost. Data can be encrypted not only with secret keys and initial vectors, but also by different block ciphers during the communication. A novel on-the-fly key expansion design is also proposed for 128-, 192-, and 256-bit keys. Our unified hardware can run both the original AES algorithm and the extended AES algorithm. The p… Show more

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Cited by 11 publications
(10 citation statements)
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References 17 publications
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“…This image square is called the table and it includes a 256 number of (0-255) and matched to the other side results [8,16]. It will add value to the simple process consists of each round of words or notes, which are created by the extension of key routine [11,17]. …”
Section: Methodsmentioning
confidence: 99%
See 1 more Smart Citation
“…This image square is called the table and it includes a 256 number of (0-255) and matched to the other side results [8,16]. It will add value to the simple process consists of each round of words or notes, which are created by the extension of key routine [11,17]. …”
Section: Methodsmentioning
confidence: 99%
“…Each round of master key is using key encryption expansion algorithm or decoding, which needs 128-byte Round Key, Figure 6 [12,20]. The development of decoding operations that are in a reverse order, compared with arranged decoding mode and therefore at the beginning of the preliminary round, followed by nine occurrences of the regular round reverse, but ends with the addition of key stage consists regular tours inverse [3,11]. 2.5 Inv.…”
Section: Shift Rows Transformationmentioning
confidence: 99%
“…From the first ASIC implementation [43] of AES, there are serials of related implementation schemes [21,42]. The best performance implementation of AES-ECB 128-bit on ASIC is Hodjat's study in [20].…”
Section: Overview Of Fpga/asicmentioning
confidence: 99%
“…From the first ASIC implementation [10] of AES, there are serials of related implementation schemes [11,12]. The best performance implementation of AES-ECB 128-bit on ASIC is Hodjat's [13].…”
Section: The Application Of Vlsi In Cryptographymentioning
confidence: 99%