A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs

Abstract

A dynamically-controlled power-gated (DCPG) FPGA architecture has recently been proposed to reduce static energy dissipation during idle periods. During a power mode transition from an off state to on state, the wakeup current drawn from power supplies causes a voltage droop on the power distribution network of a device. If not handled appropriately, this current and the associated voltage droop could cause malfunction of the design and/or the device. In DCPG FPGAs, the amount of wakeup current is not known beforehand as the structures of power-gated modules are application dependent; thus, a configurable solution is required to handle wakeup current. In this paper we propose a programmable wakeup architecture for DCPG FPGAs. The proposed solution has two levels: a fixed intra-region level and a configurable inter-region level. The architecture ensures that a power-gated module can be turned on such that the wakeup current constraints are not violated. We study the area and power overheads of the proposed solution. Our results show that the area overhead of the proposed inrush current limiting architecture is less than 2% for a power gating region of size 3x3 or 4x4 tiles, and the leakage power saved is more than 85% in a region of size 4x4 tiles.

An FPGA with power-gated switch blocks

“…In [11], a configurable architecture has been proposed to solve the inrush current problem in FPGAs supporting dynamically-controlled power gating by staggering the turn on phase of different power gating regions in a power-gated module. The proposed architecture was found to have a very small area and power overheads.…”

“…The proposed architecture was found to have a very small area and power overheads. The architecture in [11] can be used to solve the inrush current problem in our proposed architecture with small additional area and power overheads.…”

An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating

“…[21], [22] presented a configurable architecture to solve the inrush current problem in FPGAs that support DCPG by staggering the turn on phase of the PGRs in a power-gated module. The architecture in [21], [22] can be used to solve the inrush current problem in the proposed architecture in this paper with small area and power overheads. The architecture provides short turn on times.…”

“…The inrush current handling architecture in [21], [22] enables delaying the wakeup signal for each PGR using configurable and fixed delay elements. The timing for activating the isolation mechanism in our architecture (pull-down NMOS transistors) must be handled appropriately.…”

Sensing nanosecond-scale voltage attacks and natural transients in FPGAs

“…The VLSI design of FPGAs is proprietary and simulation models are unavailable, so users cannot model and simulate high-speed voltage transients in their systems. The increasing reliance on power gating complicates the dynamics further [3]. In short, FPGA system designers and users are largely in the dark about their system's voltage noise.…”