Abstract-Leakage power is an important component of the total power consumption in FPGAs built using 90 nm and smaller technology nodes. Power gating, in which regions of the chip can be powered down, has been shown to be effective at reducing leakage power. However, previous techniques focus on staticallycontrolled power gating. In this paper, we propose a modification to the fabric of an FPGA that enables dynamically-controlled power gating, in which logic clusters can be selectively powereddown at run-time. For applications containing blocks with large idle times, this could lead to significant leakage power savings. Our architecture utilizes the existing routing fabric and unused input pins of logic clusters to route the power control signals. No modifications to the existing routing algorithms are required to support the new architecture. We study the area and power tradeoffs by varying the basic architecture parameters of an FPGA, and by varying the size of the power gating regions. We also study the leakage energy savings using a model that characterizes an application in terms of its structure and behavior. We show less than 1% of area overhead for a power gating region size of 3X3 logic tiles. Using the application model, we show that up to 40% leakage energy reduction can be achieved using the proposed architecture for different application parameters, not including power dissipated by the power state controller.

Abstract-Static power consumption is an important component of the total power consumption in FPGAs built using 90 nm and smaller technology nodes. A previous study proposed powering down regions of logic blocks in an FPGA when idle to reduce the static power dissipation. This previous work did not consider powering down the switch blocks (SBs). However, the static power of SBs constitute more than 50% of an FPGA's static power. In this paper, we present an architecture that enables selectively powering down SBs along with the logic blocks during their idle periods. The potential power savings from this architecture depends on the proportion of SBs that can be powered down. We present modifications to our CAD flow to maximize the number of such SBs, and we experimentally estimate their proportion using a set of synthetic benchmark circuits. Our estimation results show that 53% to 83% of the SBs can be powered down in a functional module of size 24 × 24 tiles and an architecture power gating regions of size 4×4 tiles, leading to overall static power reductions of 70% to 84% compared to an architecture that does not support power gating.

Abstract-Negative bias temperature instability (NBTI) significantly affects nanoscale integrated circuit performance and reliability. The degradation in threshold voltage (V th ) due to NBTI is further affected by the initial value of V th from fabricationinduced process variation (PV). Addressing these challenges in embedded FPGA designs is possible, as FPGA reconfigurablility can be exploited to measure the exact timing degradation of an FPGA due to the joint effect of NBTI and PV at run time with low overhead. The gathered information can then be used to improve the run-time performance and reliability of FPGA designs without targeting the pessimistic worst case.In this paper, we present joint NBTI/PV-aware placement techniques for FPGAs, including NBTI/PV-aware timing analysis, region-based delay estimation, and a new move-acceptance procedure. To evaluate the proposed techniques, we combine PV measurements from 15 Xilinx Virtex-II Pro FPGAs with a model of NBTI. The proposed techniques reduce the effect of NBTI/PV by more than 60% for over 60% of the 15 FPGA chips used in the experiments, with a typical run-time overhead of 1.4-1.8X. The standalone move-acceptance procedure also produces good results with negligible run-time overhead, making it suitable for online FPGA compilation and optimization flows. I. INTRODUCTIONNegative bias temperature instability (NBTI) is a leading reliability challenge at the nano-scale level that causes degradation in the threshold voltage (V th ) of a PMOS transistor, which gradually increases delay. NBTI occurs when a PMOS transistor is stressed under high temperatures with V gs = −V dd , causing high oxide electric field (E ox ); this stress causes some Si-H bonds on the Si-SiO 2 interface to break, leaving unpaired valence electron in Si atoms. These broken bonds are called interface traps. The existence of such traps increases the absolute value of V th in PMOS transistors.NBTI degradation is further affected by the initial value of V th that may deviate from the nominal value due to process variation (PV). The initial value of V th determines the amount of E ox ; the smaller its initial value, the higher E ox , which increases NBTI degradation. However, the joint NBTI/PV effect, i.e., combining initial V th with the expected degradation due to NBTI, shows that variation in V th is always the dominating factor, which means that transistors with smaller initial V th will have smaller V th even after NBTI degradation.Variations in V th are expected to further increase according to the ITRS [1]. Addressing the joint NBTI/PV effect becomes increasingly critical.The regular structure of FPGAs and their reconfigurability can be exploited to measure the joint effect of PV and NBTI at run time. The results can be used to optimize circuit placement and routing with awareness of NBTI and PV effects to improve

Abstract-Leakage power is an important component of the total power consumption in FPGAs built using 90 nm and smaller technology nodes. Power gating was shown to be effective at reducing leakage power. Previous techniques focus on turning off unused FPGA resources at configuration time; the benefit of this approach depends on resources utilization. In this paper, we present an FPGA architecture that enables dynamicallycontrolled power gating, in which FPGA resources can be selectively powered-down at run-time. This could lead to significant overall energy savings for applications having modules with long idle times. We also present a CAD flow that can be used to map applications to the proposed architecture. We study the area and power trade-offs by varying the different FPGA architecture parameters and power gating granularity. The proposed CAD flow is used to map a set of benchmark circuits that have multiple power-gated modules to the proposed architecture. Power savings of up to 83% are achievable for these circuits. Finally, we study a control system of a robot that is used in endoscopy. Using the proposed architecture combined with clock gating results in up to 19% energy savings in this application.

A dynamically-controlled power-gated (DCPG) FPGA architecture has recently been proposed to reduce static energy dissipation during idle periods. During a power mode transition from an off state to on state, the wakeup current drawn from power supplies causes a voltage droop on the power distribution network of a device. If not handled appropriately, this current and the associated voltage droop could cause malfunction of the design and/or the device. In DCPG FPGAs, the amount of wakeup current is not known beforehand as the structures of power-gated modules are application dependent; thus, a configurable solution is required to handle wakeup current. In this paper we propose a programmable wakeup architecture for DCPG FPGAs. The proposed solution has two levels: a fixed intra-region level and a configurable inter-region level. The architecture ensures that a power-gated module can be turned on such that the wakeup current constraints are not violated. We study the area and power overheads of the proposed solution. Our results show that the area overhead of the proposed inrush current limiting architecture is less than 2% for a power gating region of size 3x3 or 4x4 tiles, and the leakage power saved is more than 85% in a region of size 4x4 tiles.