A Constant Time Full Hardware Implementation of Streamlined NTRU Prime

Marotzke, Adrian

doi:10.1007/978-3-030-68487-7_1

Cited by 8 publications

(2 citation statements)

References 11 publications

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“…We present our hardware design and optimization for the polynomial inversion in this section. In 2020, Marotzke [Mar20] had reported an implementation for the polynomial inversion required in NTRU Prime, a post-quantum KEM. The inversion module utilizes Bernstein and Yang's extGCD algorithm [BY19] optimized to perform inversions of polynomials of degree 760 with coefficients in prime fields, where the arithmetic takes place in Digital Signal Processor (DSP) units.…”

Section: Polynomial Inversionmentioning

confidence: 99%

Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware

Richter-Brockmann

Chen

Ghosh

et al. 2021

TCHES

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BIKE is a Key Encapsulation Mechanism selected as an alternate candidate in NIST’s PQC standardization process, in which performance plays a significant role in the third round. This paper presents FPGA implementations of BIKE with the best area-time performance reported in literature. We optimize two key arithmetic operations, which are the sparse polynomial multiplication and the polynomial inversion. Our sparse multiplier achieves time-constancy for sparse polynomials of indefinite Hamming weight used in BIKE’s encapsulation. The polynomial inversion is based on the extended Euclidean algorithm, which is unprecedented in current BIKE implementations. Our optimized design results in a 5.5 times faster key generation compared to previous implementations based on Fermat’s little theorem.Besides the arithmetic optimizations, we present a united hardware design of BIKE with shared resources and shared sub-modules among KEM functionalities. On Xilinx Artix-7 FPGAs, our light-weight implementation consumes only 3 777 slices and performs a key generation, encapsulation, and decapsulation in 3 797 μs, 443 μs, and 6 896 μs, respectively. Our high-speed design requires 7 332 slices and performs the three KEM operations in 1 672 μs, 132 μs, and 1 892 μs, respectively.

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Section: Polynomial Inversionmentioning

confidence: 99%

Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware

Richter-Brockmann

Chen

Ghosh

et al. 2021

TCHES

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“…Various works exist in the literature ( [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21]) that present optimized implementations of either a PKE/KEM or a signature scheme. While such works show how to implement a given PQC algorithm optimally, they do not take real-world applications (i.e., both PKE/KEM and signature) into consideration.…”

Section: Introductionmentioning

confidence: 99%

A Unified Cryptoprocessor for Lattice-Based Signature and Key-Exchange

Aikata

Mert

Jacquemin

et al. 2023

IEEE Trans. Comput.

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We propose design methodologies for building a compact, unified and programmable cryptoprocessor architecture that computes post-quantum key agreement and digital signature. Synergies in the two types of cryptographic primitives are used to make the cryptoprocessor compact. As a case study, the cryptoprocessor architecture has been optimized targeting the signature scheme 'CRYSTALS-Dilithium' and the key encapsulation mechanism (KEM) 'Saber', both finalists in the NIST's post-quantum cryptography standardization project. The programmable cryptoprocessor executes key generations, encapsulations, decapsulations, signature generations, and signature verifications for all the security levels of Dilithium and Saber. On a Xilinx Ultrascale+ FPGA, the proposed cryptoprocessor consumes 18,406 LUTs, 9,323 FFs, 4 DSPs, and 24 BRAMs. It achieves 200 MHz clock frequency and finishes CCA-secure key-generation/encapsulation/decapsulation operations for LightSaber in 29.6/40.4/ 58.3µs; for Saber in 54.9/69.7/94.9µs; and for FireSaber in 87.6/108.0/139.4µs, respectively. It finishes key-generation/sign/verify operations for Dilithium-2 in 70.9/151.6/75.2µs; for Dilithium-3 in 114.7/237/127.6µs; and for Dilithium-5 in 194.2/342.1/228.9µs, respectively, for the best-case scenario. On UMC 65nm library for ASIC the latency is improved by a factor of two due to a 2× increase in clock frequency.

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Benchmarking and Analysing the NIST PQC Lattice-Based Signature Schemes Standards on the ARM Cortex M7

Howe¹,

Westerbaan

2023

Lecture Notes in Computer Science

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A Constant Time Full Hardware Implementation of Streamlined NTRU Prime

Cited by 8 publications

References 11 publications

Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware

Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware

A Unified Cryptoprocessor for Lattice-Based Signature and Key-Exchange

Benchmarking and Analysing the NIST PQC Lattice-Based Signature Schemes Standards on the ARM Cortex M7

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