A Continuous Time ¿¿ ADC for Voice Coding with 92dB DR in 45nm CMOS

Dorrer, L.; Kuttner, F.; Santner, A.; Kropf, C.; Puaschitz, T.; Hartig, Thomas; Punzenberger, M.

doi:10.1109/isscc.2008.4523277

Cited by 15 publications

(10 citation statements)

References 5 publications

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“…11 (data from [3]). This shows that this work achieves the smallest chip area among Σ∆ ADCs implemented in low-cost mature CMOS technologies (feature size >0.13 µm) with similar noise performance [4][5][6], and its area is comparable to state-of-theart Σ∆ ADCs implemented in more expensive deep-submicron technologies (feature size <0.13 µm) [7][8][9].…”

Section: Experimental Results and Benchmarkmentioning

confidence: 99%

A 0.1-mm<sup>2</sup> 3-channel area-optimized ΣΔ ADC in 0.16-µm CMOS with 20-kHz BW and 86-dB DR

Foti

Veldhoven

2013

2013 Proceedings of the ESSCIRC (ESSCIRC)

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Front-ends for automotive sensors must digitize multiple channels with high resolution while minimizing their silicon area to save costs. Both channel latency and inter-channel gain mismatch must be minimized to be able to serve multiple sensor applications, ranging from ABS to power steering, with the same front-end. The proposed Σ∆ Σ∆ Σ∆ Σ∆ ADC simultaneously digitizes 3 channels, each with a DR of 86 dB over a 20-kHz BW using a 75-MHz clock. Channel latency is <40 ns and interchannel gain mismatch is <0.2%. The ADC occupies only 0.1 mm 2 in a 0.16-µ µ µ µm CMOS process. The small area is enabled by channel multiplexing, allowing component sharing among the channels, and by the large oversampling ratio (OSR), allowing for smaller capacitors. I. INTRODUCTION As the number of sensors in cars is increasing rapidly [1]and power is readily available from the car battery, automotive sensor roadmaps are mainly driven by cost rather than power. This puts pressure on the silicon area allowed for the sensor front-end. At the same time, to get more and higher-quality signal processing, digitization of the sensor channels is required. Moreover, to reduce time-to-market of this increasing number of sensors, the front-end must be flexible enough to be re-used for different sensors. This calls for smarter multi-purpose front-end implementations, which do more with less silicon area and can still cover multiple automotive sensor applications, like speed and angular sensors for ABS, power steering, transmission and motor management.

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Section: Experimental Results and Benchmarkmentioning

confidence: 99%

A 0.1-mm<sup>2</sup> 3-channel area-optimized ΣΔ ADC in 0.16-µm CMOS with 20-kHz BW and 86-dB DR

Foti

Veldhoven

2013

2013 Proceedings of the ESSCIRC (ESSCIRC)

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“…The CSB OTA-C integrator will provide a high input impedance and also high linearity even with a single-ended input. The second and third integrators are the conventional active-RC integrators [9][10][11].…”

Section: System Architecturementioning

confidence: 99%

“…Also, in order to be driven directly by the microphone, the first integrator must have high input impedance. In a conventional CT SDM, the first integrator is typically implemented as an active RC filter to achieve high linearity, but this results in low input impedance [9][10][11].…”

Section: Integrator Topologies With High Input Impedance and High Linmentioning

confidence: 99%

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A microphone readout interface with 74-dB SNDR

Odame

2014

Analog Integr Circ Sig Process

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A continuous-time (CT) sigma-delta modulator (SDM) for condenser microphone readout interfaces is presented in this paper. The CT SDM can accommodate a single-ended input and has high input impedance, so that it can be directly driven by a single-ended condenser microphone. A current-sensing boosted OTA-C integrator with capacitive feedforward compensation is employed in the CT SDM to achieve high input impedance and high linearity with low power consumption. Fabricated in a 0:35-lm complementary metal-oxide-semiconductor (CMOS) process, a circuit prototype of the CT SDM achieves a peak signal-to-noise-and-distortion ratio of 74.2 dB, with 10-kHz bandwidth and 801-lW power consumption.

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“…It is also used in analog-to-digital conversion [35][36][37][38], in phase-locked loops [39][40][41][42][43][44][45][46][47][48][49], and as a source to generate dithering signals [50][51][52][53][54][55][56], to segment the DAC further [57,58] and in multiple-input, multiple-output transceivers [59], etc. All of the above signal processing blocks are used for narrow-, wideand ultra-wide-band applications like digital audio [60][61][62], handsets [63][64][65], biomedical [66,67], TV [68][69][70], digital radio tuners [71,72] and wireless infrastructures [73][74][75].…”

Section: Introductionmentioning

confidence: 99%

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Afzal

2015

Linköping Studies in Science and Technology. Dissertations

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Papers A and C are reprinted with permission from IEEE.Cover figure is an illustration of the digital cascaded error-feedback modulator.Printed by LiU-Tryck, Linköping, Sweden 2014 To my parents and teachers AbstractA number of state-of-the-art low power consuming digital delta-sigma modulator (∆Σ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ∆Σ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ∆Σ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.Further on, it is described that the architectural properties of a unit elementbased DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.All of the designs are subjected to rigorous analysis and are described mathev vi Abstract matically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry. Populärvetenskaplig sammanfattning vii viiiPopulärvetenskaplig sammanfattning I denna avhandling presenteras e...

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A Continuous Time ¿¿ ADC for Voice Coding with 92dB DR in 45nm CMOS

Cited by 15 publications

References 5 publications

A 0.1-mm<sup>2</sup> 3-channel area-optimized ΣΔ ADC in 0.16-µm CMOS with 20-kHz BW and 86-dB DR

A 0.1-mm<sup>2</sup> 3-channel area-optimized ΣΔ ADC in 0.16-µm CMOS with 20-kHz BW and 86-dB DR

A microphone readout interface with 74-dB SNDR

Complexity and Power Reduction in Digital Delta-Sigma Modulators

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A Continuous Time ¿¿ ADC for Voice Coding with 92dB DR in 45nm CMOS

Cited by 15 publications

References 5 publications

A 0.1-mm<sup>2</sup> 3-channel area-optimized &#x03A3;&#x0394; ADC in 0.16-&#x00B5;m CMOS with 20-kHz BW and 86-dB DR

A 0.1-mm<sup>2</sup> 3-channel area-optimized &#x03A3;&#x0394; ADC in 0.16-&#x00B5;m CMOS with 20-kHz BW and 86-dB DR

A microphone readout interface with 74-dB SNDR

Complexity and Power Reduction in Digital Delta-Sigma Modulators

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A 0.1-mm<sup>2</sup> 3-channel area-optimized ΣΔ ADC in 0.16-µm CMOS with 20-kHz BW and 86-dB DR

A 0.1-mm<sup>2</sup> 3-channel area-optimized ΣΔ ADC in 0.16-µm CMOS with 20-kHz BW and 86-dB DR