A Continuous-Time Delta-Sigma Modulator Using a Modified Instrumentation Amplifier and Current Reuse DAC for Neural Recording

Nikas, Antonios; Jambunathan, Sreenivas; Klein, Leonhard; Voelker, Matthias; Ortmanns, Maurits

doi:10.1109/jssc.2019.2931811

Cited by 35 publications

(5 citation statements)

References 25 publications

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“…The conceptual block diagram of DC-coupled

based CT-DSM with the resistive feedback digital-to-analog convertor (RDAC) is shown in Figure 12A . The DC-coupled DSM ( Nikas et al, 2019 ; Moeinfard and Kassiri, 2022 ) has a higher input impedance than ac-couple DSM with chopper topology ( Johnson et al, 2017 ; Bang et al, 2018 ; Zhao et al, 2019 ) and conventional

based CT-DSM ( Schoofs et al, 2007 ; Sarhangnejad et al, 2011 ; Huang et al, 2015 ) (implementing a summing node at the output of the integrator). The traditional way to improve the linearity of

is to achieve it through source degeneration technology ( Wattanapanitch et al, 2007 ), but this will still cause the output of Gm to saturate in the case of a larger input signal.…”

Section: Anti-artifacts Technologymentioning

confidence: 99%

Anti-artifacts techniques for neural recording front-ends in closed-loop brain-machine interface ICs

Chen,

Liu,

Wan

et al. 2024

Front. Neurosci.

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In recent years, thanks to the development of integrated circuits, clinical medicine has witnessed significant advancements, enabling more efficient and intelligent treatment approaches. Particularly in the field of neuromedical, the utilization of brain-machine interfaces (BMI) has revolutionized the treatment of neurological diseases such as amyotrophic lateral sclerosis, cerebral palsy, stroke, or spinal cord injury. The BMI acquires neural signals via recording circuits and analyze them to regulate neural stimulator circuits for effective neurological treatment. However, traditional BMI designs, which are often isolated, have given way to closed-loop brain-machine interfaces (CL-BMI) as a contemporary development trend. CL-BMI offers increased integration and accelerated response speed, marking a significant leap forward in neuromedicine. Nonetheless, this advancement comes with its challenges, notably the stimulation artifacts (SA) problem inherent to the structural characteristics of CL-BMI, which poses significant challenges on the neural recording front-ends (NRFE) site. This paper aims to provide a comprehensive overview of technologies addressing artifacts in the NRFE site within CL-BMI. Topics covered will include: (1) understanding and assessing artifacts; (2) exploring the impact of artifacts on traditional neural recording front-ends; (3) reviewing recent technological advancements aimed at addressing artifact-related issues; (4) summarizing and classifying the aforementioned technologies, along with an analysis of future trends.

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“…The conceptual block diagram of DC-coupled

based CT-DSM ( Schoofs et al, 2007 ; Sarhangnejad et al, 2011 ; Huang et al, 2015 ) (implementing a summing node at the output of the integrator). The traditional way to improve the linearity of

is to achieve it through source degeneration technology ( Wattanapanitch et al, 2007 ), but this will still cause the output of Gm to saturate in the case of a larger input signal.…”

Section: Anti-artifacts Technologymentioning

confidence: 99%

Anti-artifacts techniques for neural recording front-ends in closed-loop brain-machine interface ICs

Chen,

Liu,

Wan

et al. 2024

Front. Neurosci.

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show abstract

“…Another new architecture uses a continuous-time delta-sigma modulator (CTDSM) as the recording front end (RFE), and the researcher establishes the structure based on a secondorder CTDSM (Nikas et al, 2019). As shown in Figure 3C, it has a cascaded integrator and a feedforward compensation architecture with distributed feed-in paths and a single-bit quantizer.…”

Section: Neural Recordingmentioning

confidence: 99%

Advances in Neural Recording and Stimulation Integrated Circuits

Liu

Mao

et al. 2021

Front. Neurosci.

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In the past few decades, driven by the increasing demands in the biomedical field aiming to cure neurological diseases and improve the quality of daily lives of the patients, researchers began to take advantage of the semiconductor technology to develop miniaturized and power-efficient chips for implantable applications. The emergence of the integrated circuits for neural prosthesis improves the treatment process of epilepsy, hearing loss, retinal damage, and other neurological diseases, which brings benefits to many patients. However, considering the safety and accuracy in the neural prosthesis process, there are many research directions. In the process of chip design, designers need to carefully analyze various parameters, and investigate different design techniques. This article presents the advances in neural recording and stimulation integrated circuits, including (1) a brief introduction of the basics of neural prosthesis circuits and the repair process in the bionic neural link, (2) a systematic introduction of the basic architecture and the latest technology of neural recording and stimulation integrated circuits, (3) a summary of the key issues of neural recording and stimulation integrated circuits, and (4) a discussion about the considerations of neural recording and stimulation circuit architecture selection and a discussion of future trends. The overview would help the designers to understand the latest performances in many aspects and to meet the design requirements better.

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“…The design reported in [25] combines very good area and power consumption with low noise, but does not feature full-band recording. The direct conversion architectures in [21], [24] allow to have infinite dc input impedance without a booster, but the area consumption is larger (however with the ADC already included) despite using a smaller CMOS node in [21] and furthermore the input referred noise is significantly larger.…”

Section: State-of-the-art Comparisonmentioning

confidence: 99%

A Chopped Neural Front-End Featuring Input Impedance Boosting With Suppressed Offset-Induced Charge Transfer

Reich

Sporer

Ortmanns

2021

IEEE Trans. Biomed. Circuits Syst.

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Modern neuromodulation systems typically provide a large number of recording and stimulation channels, which reduces the available power and area budget per channel. To maintain the necessary input-referred noise performance despite growingly rigorous area constraints, chopped neural front-ends are often the modality of choice, as chopperstabilization allows to simultaneously improve (1/f) noise and area consumption. The resulting issue of a drastically reduced input impedance has been addressed in prior art by impedance boosters based on voltage buffers at the input. These buffers precharge the large input capacitors, reduce the charge drawn from the electrodes and effectively boost the input impedance. Offset on these buffers directly translates into charge-transfer to the electrodes, which can accelerate electrode aging. To tackle this issue, a voltage buffer with ultra-low time-averaged offset is proposed, which cancels offset by periodic reconfiguration, thereby minimizing unintended charge transfer. This article explains the background and circuit design in detail and presents measurement results of a prototype implemented in a 180 nm HV CMOS process. The measurements confirm that signal-independent, buffer offset induced charge transfer occurs and can be mitigated by the presented buffer reconfiguration without adversely affecting the operation of the input impedance booster. The presented neural recorder front-end achieves state of the art performance with an area consumption of 0.036 mm 2 , an input referred noise of 1.32 µVrms (1 Hz to 200 Hz) and 3.36 µVrms (0.2 kHz to 10 kHz), power consumption of 13.7 µW from 1.8 V supply, as well as CMRR and PSRR ≥83 dB at 50 Hz.

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A Continuous-Time Delta-Sigma Modulator Using a Modified Instrumentation Amplifier and Current Reuse DAC for Neural Recording

Cited by 35 publications

References 25 publications

Anti-artifacts techniques for neural recording front-ends in closed-loop brain-machine interface ICs

Anti-artifacts techniques for neural recording front-ends in closed-loop brain-machine interface ICs

Advances in Neural Recording and Stimulation Integrated Circuits

A Chopped Neural Front-End Featuring Input Impedance Boosting With Suppressed Offset-Induced Charge Transfer

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