A conventional 45nm CMOS node low-cost platform for general purpose and low power applications

Bœuf, F.; Arnaud, F.; Basso, M.-T.; Sotta, D.; Wacquant, F.; Rosa, J.; Bicais-Lepinay, N.; Bernard, H.; Bustos, J.; Manakli, S.; Gaillardin, M.; Grant, John M.; Skotnicki, T.; Tavel, B.; Duriez, B.; Bidaud, M.; Gouraud, P.; Chaton, C.; Morin, P.; Todeschini, J.; Jurdit, M.; Pain, Laurent; DeJonghe, V.; El-Farhane, R.; Jullian, S.

doi:10.1109/iedm.2004.1419177

Cited by 39 publications

(19 citation statements)

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“…These values are an order of magnitude smaller than ΔV T values of the 20 nm gate length bulk silicon transistors reported by Boeuf [8] and others [9][10][11][12]. The amount of DIBL is 114 mV/V for the NMOS and 69 mV/V for the PMOS transistors with 4 nm radius and 7 nm effective channel length.…”

Section: Characteristics Of the Selected Nmos And Pmos Transistorsmentioning

confidence: 60%

Single Work Function Silicon Nanowire MOS Transistors

Bindal

Hamedi-Hagh

2016

Silicon Nanowire Transistors

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In the first chapter of this book, SNTs with dual work function gates were designed and their device characteristics were examined. Later in the same chapter, basic digital CMOS gates were built; their circuit performance, power dissipation, and layout characteristics were analyzed; basic SNT processing steps were shown. A dual work function CMOS technology requires the use of different metals in NMOS and PMOS transistor gates. Finding the appropriate metals that match exactly to the work function values found in this study may often be a difficult enterprise as it may require alloys for gate material or incompatible metals with the SNT processing.One way to reduce the set of problems associated with dual metals is to use a single metal gate. Therefore, this chapter is dedicated to design NMOS and PMOS transistors with a single work function metal gate, and furthermore use these transistors in designing CMOS circuits.As in Chapter 1, this chapter will also introduce the design criteria for SNTs that use a single metal gate, show the design flow to select optimum device dimensions for both NMOS and PMOS transistors, and analyze speed, power dissipation and layout area characteristics of various CMOS logic gates and mega cells that use these devices.The design criteria for the single work function NMOS and PMOS SNTs are very similar to what has been applied to the dual work function SNTs.1. NMOS and PMOS transistors need to have at least 300 mV threshold voltage for 1 V CMOS circuit operation 2. The static OFF current has to be under 1 pA in either NMOS or PMOS transistor

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Section: Characteristics Of the Selected Nmos And Pmos Transistorsmentioning

confidence: 60%

Single Work Function Silicon Nanowire MOS Transistors

Bindal

Hamedi-Hagh

2016

Silicon Nanowire Transistors

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“…However strained-Si (s-Si) technologies have already demonstrated on current enhancements of 20% to 30% for sub-50nm channel lengths [12][13][14], in fact a correlation between the mobility and I DS improvements has been predicted by means of simple flux-theory arguments [15], confirmed by numerical simulations [16][17][18][19][20], as well as observed in the experiments [12-14, 21, 22]. The on-current enhancements achieved with the strain engineering have been so remarkable that the strain has sometimes replaced rather than simply augmented the geometrical scaling, as it can be seen in Fig.…”

Section: Introductionmentioning

confidence: 99%

Semi-classical transport modelling of CMOS transistors with arbitrary crystal orientations and strain engineering

et al. 2009

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This paper reviews the basic methodologies and models used in the semi-classical modelling of CMOS transistors in the framework of the nowadays generalized scaling scenario. The capabilities to describe devices with arbitrary crystal orientations and strain configurations are discussed. Several simulation results are illustrated and compared to the experiments to assess the understanding of the underlying physics and the predictive capabilities of the models. A case study concerning the drain currents in nano-scale uniaxially strained MOSFETs is presented and it shows how the strain engineering may change the traditional on-current disadvantage of the p-MOS compared to the n-MOS transistors.

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“…For an n-input gate, there are 2n timing arcs. 6 Due to different parasitics, as well as PMOS/NMOS asymmetries, these timing arcs can have different delay values associated with them. For instance, Table II shows the delay values for the same input slew and load capacitance pair for different timing arcs of a NAND2X2 cell from the Artisan TSMC 130-nm library.…”

Section: Transistor-level Gate-length Biasingmentioning

confidence: 99%

“…However, we have found the proposed technique to substantially reduce leakage for the two 130-nm and two 90-nm industrial processes that we investigated. Recent reports from leading integrated device manufacturers (IDMs) indicate that SCE continues to dominate V th roll-off characteristics at the 65-and 45-nm technology nodes [6], [16], [19], [20]. However, we note that the V th roll-off curve must be understood to assess the feasibility of this approach and to determine reasonable increases for the gate length.…”

Section: Introductionmentioning

confidence: 99%

Gate-length biasing for runtime-leakage control

Gupta

Kahng

Sharma

et al. 2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Leakage power has become one of the most critical design concerns for the system level chip designer. While lowered supplies (and consequently, lowered threshold voltage) and aggressive clock gating can achieve dynamic power reduction, these techniques increase the leakage power and, therefore, causes its share of total power to increase. Manufacturers face the additional challenge of leakage variability: Recent data indicate that the leakage of microprocessor chips from a single 180-nm wafer can vary by as much as 20×. Previously proposed techniques for leakage-power reduction include the use of multiple supply and gate threshold voltages, and the assignment of input values to inactive gates, such that leakage is minimized.The additional design space afforded by the biasing of device gate lengths to reduce chip leakage power and its variability is studied. It is well known that leakage power decreases exponentially and delay increases linearly with increasing gate length. Thus, it is possible to increase gate length only marginally to take advantage of the exponential leakage reduction, while impairing performance only linearly. From a design-flow standpoint, the use of only slight increases in gate length preserves both pin and layout compatibility; therefore, the authors' technique can be applied as a postlayout enhancement step. The authors apply gate-length biasing only to those devices that do not appear in critical paths, thus assuring zero or negligible degradation in chip performance. To highlight the value of the technique, the multithreshold voltage technique, which is widely used for leakage reduction, is first applied and then gate-length biasing is used to show further reduction in leakage.Experimental results show that gate-length biasing reduces leakage by 24%-38% for the most commonly used cells, while incurring delay penalties of under 10%. Selective gate-length biasing at the circuit level reduces circuit leakage by up to 30% with no delay penalty. Leakage variability is reduced significantly by up to 41%, which may lead to substantial improvements in the manufacturing yield and the product cost. The use of gate-length biasing for leakage optimization of cell instances is also assessed, in which: 1) not all timing arcs are timing critical and/or 2) the rise and fall transitions are not both timing critical at the same time.

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A conventional 45nm CMOS node low-cost platform for general purpose and low power applications

Cited by 39 publications

References 0 publications

Single Work Function Silicon Nanowire MOS Transistors

Single Work Function Silicon Nanowire MOS Transistors

Semi-classical transport modelling of CMOS transistors with arbitrary crystal orientations and strain engineering

Gate-length biasing for runtime-leakage control

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