A converging route towards very high frequency, mechanically flexible, and performance stable integrated electronics

Abstract

The ability to realize flexible circuits integrating sensing, signal processing, and communicating capabilities is of central importance for the development of numerous nomadic applications requiring foldable, stretchable, and large area electronics. A key challenge is, however, to combine high electrical performance (i.e., millimeter wave, low noise electronics) with mechanical flexibility required for chip form adaptivity in addition to highly stable electrical performance upon deformation. Here, we describe a solution based on ultimate thinning and transfer onto a plastic foil of high frequency CMOS devices initially processed on conventional silicon-on-insulator wafers. We demonstrate a methodology relying on neutral plane engineering to provide high performance stability upon bending, by locating the active layer, i.e., the transistor channel, at the neutral fiber of the flexible system. Following this strategy, record frequency performance of flexible n-MOSFETs, featuring f T /f MAX of 120/145 GHz, is reported with relative variations limited to less than 5% even under aggressive bending on cylinders with curvature radii down to 12.5 mm. V

Flexible and Stretchable Microwave Electronics: Past, Present, and Future Perspective

“…[61,62] Figure 2e presents the process flow of a DBG process, which alleviates the problematic dispersing process after conventional grinding. [44] The thickness of the semiconductor layer can be reduced to sub-5 µm if the semiconductor wafers have an etch-stop layer like the epitaxial GaN layer in GaN-on-Si wafer [63,64] or the BOX layer in SOI wafer [45,65] (see Figure 2f as an example). Since the major effort of thinning processes is carried on the backside surface, the front side surface of the semiconductor wafer can be fully protected, which is advantageous for postdevice fabrication, i.e., the transistors and circuits have been fabricated on the semiconductor wafer before the thinning process.…”

“…Besides reports of the undercut etching method to release a layer of fabricated devices from Si, a number of studies on direct thinning of industry foundry fabricated deep-sub-micrometer rigid Si RF MOSFET chip to attain mechanically flexible integrated chips were reported. [45,59,60,65,[83][84][85][86] Benefitting from the small feature sizes of the Si RF MOSFETs, the high-frequency properties of rigid form MOSFETs were passed along to flexible form devices. For example, flexible Si RF MOSFETs at 0.13 µm node show an f T of 118 GHz on a plastic substrate via thinning bulk Si wafer.…”

“…[31,87] To further reduce the thickness of thinned Si chips, SOIbased RF MOSFETs chips by using BOX as their etch-stop layer were also studied. [45,66,84,85,88] In this method, after thinning the Si handling substrate of SOI down to ≈20-50 µm, the remaining Si substrate can be removed using selective etchants like XeF 2 with the front side protected. Flexible Si RF MOSFETs at 65 nm node, as thin as 5.7 µm, including 145 nm BOX layer, 60 nm Si active layer, and ≈5.5 µm interconnection layer, have been fabricated with the multistage thinning process (see Figures 2f and 4d), which showed record-high f T and f max of 150 and 160 GHz, respectively, as a result of the highly scaled CMOS technology.…”

<strong>Material-integrated Intelligent Systems: A Review on State of the Art, Challenges and Trends</strong>

“…But even under less critical conditions, and once part production is survived, service loads have to be sustained: Locally, these may be increased by mismatches in thermal (coefficient of thermal expansion) and mechanical properties (Young's modulus) of the embedded system and host material, as several authors have pointed out [12,13]. To compensate mechanical loads originating from such misadjustment, stretchable and flexible electronics are being researched [14].…”

Substrate Engineering of Inductors on SOI for Improvement of Q-Factor and Application in LNA

“…Thus, optimizing the substrate is a possible pathway for better RF circuit operation. In previous studies, improvement of electrical performance of RF devices has been reported by complete removal of handler substrate on SOI wafer and transfer onto thin flexible substrate [10]- [15]. While this approach has been shown to work efficiently, some of the drawbacks are higher number of steps in fabrication, possible RF losses in bonding material, mechanical weakening and overall cost of treatment.…”