A cost-efficient high-speed 12-bit pipeline ADC in 0.18-/spl mu/m digital CMOS

Andersen, T.N.; Hernes, B.; Briskemyr, A.; Telsto, F.; Bjornsen, J.; Bonnerud, T.E.; Moldsvor, O.

doi:10.1109/jssc.2005.847519

Cited by 57 publications

(12 citation statements)

References 4 publications

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“…This speed is comparable with many high-voltage SC pipelined ADC[8],[9]. A recent design[24] achieves the fastest operation at 200 MS/s by partially switching off the opamp.…”

mentioning

confidence: 82%

“…In portable systems, low power consumption is even more important for extending the battery life. Among many ADC architectures, pipelined ADCs have proven to be very efficient for meeting the above requirements of high speed, medium resolution, and low power consumption [4]- [9]. The reason for their efficiency is mainly the concurrent operation of the pipelined stages.…”

Section: Introductionmentioning

confidence: 99%

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A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture

Cheung²,

Luong

2007

IEEE J. Solid-State Circuits

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A 1-V, 8-bit pipelined ADC is realized using multi-phase switched-opamp (SO) technique. A novel loading-free architecture is proposed to reduce the capacitive loading and to improve the speed in low-voltage SO circuits. Employing the proposed loading-free pipelined ADC architecture together with double-sampling technique and a fast-wake-up dual-input-dual-output switchable opamp, the ADC achieves 100-MS/s conversion rate, which to our knowledge is the fastest ADC ever reported at 1-V supply using SO technique, with performance comparable to that of many high-voltage switched-capacitor (SC) ADCs. Implemented in a 0.18-m CMOS process, the ADC obtains a peak SNR of 45.2 dB, SNDR of 41.5 dB, and SFDR of 52.6 dB. Measured DNL and INL are 0.5 LSB and 1.1 LSB, respectively. The chip dissipates only 30 mW from a 1-V supply.

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“…This speed is comparable with many high-voltage SC pipelined ADC[8],[9]. A recent design[24] achieves the fastest operation at 200 MS/s by partially switching off the opamp.…”

mentioning

confidence: 82%

Section: Introductionmentioning

confidence: 99%

A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture

Cheung²,

Luong

2007

IEEE J. Solid-State Circuits

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show abstract

“…The time gap between T2 and T3 is the intrinsic request from the non-overlapping clocks. The time gap between T1 and T2 ensures that the charge injection from the feedback switch is signal independent, which in turn improves the sampling linearity [32]. The time gap between T3 and T4 avoids the large voltage peak seen by ADC during the tracking period.…”

Section: B Sc C2v With Reference Capacitormentioning

confidence: 99%

“…The total noise PSD of opamp can be written as [15] S amp = S amp,th × 1 + f k f (32) where S amp is the total input-referred PSD of opamp, and f k is the corner frequency of 1/f noise. The 1/f noise dominates the PSD when the concerned frequency is lower than f k .…”

Section: B Flicker Noisementioning

confidence: 99%

Design and Implementation of a 46-kS/s CMOS SC Dual-Mode Capacitive Sensor Interface With 50-dB SNR and 0.7% Nonlinearity

Wang

Dehollain

2015

IEEE Sensors J.

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This paper presents the design and implementation of a 46-kS/s CMOS switch-capacitor dual-mode capacitive sensor interface circuit for inkjet-printed capacitive humidity sensors. The specifications of the interface circuit, which includes a capacitance-to-voltage (C2V) converter combined with an analog-to-digital converter (ADC), are optimized at system level, emphasizing the C2V operation followed by the data converter. A closed form of the maximum output range of a single-stage C2V is provided to prevent cascade amplification. The gain-boosting technique is utilized in the operational transconductance amplifier design to improve the closed-loop linearity. The correlated double sampling technique attenuates the dc offset and low-frequency flicker noise from C2V. A 10-b successive approximation register ADC digitizes the output of C2V. The total area of the digital-to-analog (DAC) array is limited not only by the matching behavior, but also by the noise performance of C2V. The rail-to-rail ability is required to render the compatibility with various possible sensor inputs. A single-ended cascaded binary-weighted capacitive DAC is used to implement the charge redistribution binary search algorithm. The circuit is implemented in a 0.18-µm CMOS technology and occupies an area of 1.2 mm 2 . The tested prototype shows 0.69% nonlinearity in mode 1 and 1.38% nonlinearity in mode 2. The SNR of mode 1 is 50.1 dB and that of mode 2 is 36.5 dB, which meets the specification of 7.32 b in mode 1 and 5.32 b in mode 2. The total power consumption of the capacitive sensor interface is 70 µW.Index Terms-Capacitive sensor interface, C2V, SAR ADC, CDS, opamp, noise optimization, power-efficient system.

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“…So the design target is a low power high-performance CMOS ADC, of which the resolution is Among various ADC architectures, pipelined converters could provide a good tradeoff between the performance and power consumption. Recently reported results also indicate that the pipeline architecture is cost-efficient [3] and suitable for the deep sub-micrometer digital CMOS technologies [4,5].…”

Section: Adc Architecturementioning

confidence: 99%

Design of an ADC for subsampling video applications

Zeng

Zhang

et al. 2006

Analog Integr Circ Sig Process

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This paper describes a 10 bit 30 Msample/s (MSPS) CMOS analog-to-digital converter (ADC) for highspeed signal processing, especially for subsampling applications, for example digital video broadcasting over cable (DVB-C), terrestrial (DVB-T) and handheld (DVB-H) systems. The proposed pipelined ADC shows a good figure-ofmerit (FoM). It adopts a power efficient amplifier sharing technique, a symmetrical gate-bootstrapping technique with modified timing for the bottom-sampling switch of a wideband sample-and-hold (S/H) circuit, a proposed stable highswing bias circuit for a wide-swing gain-boosting telescopic amplifier. The measured differential and integral nonlinearities of the prototype in a 0.25-µm CMOS technology show less than 0.4 least significant bit (LSB) and 0.85 LSB respectively at full sampling rate. The ADC exhibits higher than 9 effective number of bits (ENOB) for input frequencies up to about 60 MHz, which is the fourfold Nyquist rate (fs/2), at 30 MSPS. The ADC consumes 60 mW from a 3-V supply and occupies about 1.36 mm 2 .

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A cost-efficient high-speed 12-bit pipeline ADC in 0.18-/spl mu/m digital CMOS

Cited by 57 publications

References 4 publications

A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture

A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture

Design and Implementation of a 46-kS/s CMOS SC Dual-Mode Capacitive Sensor Interface With 50-dB SNR and 0.7% Nonlinearity

Design of an ADC for subsampling video applications

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