A Countermeasure against Differential Power Analysis based on Random Delay Insertion

Bucci, Marco; Luzzi, R.; Guglielmo, M.; Trifiletti, Alessandro

doi:10.1109/iscas.2005.1465395

Cited by 59 publications

(28 citation statements)

References 15 publications

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“…Masking and randomized masking (Wang and Ha, 2013) is common method to prevent DPA. Balanced Load Dual Rail CMOS (Sokolov et al, 2005;Batina et al, 2005;Kulikowski et al, 2005;Tiri and Verbauwhede, 2005;Bucci et al, 2005), where gates are balanced so that load switching capacitance is same. This has significant area and power overhead.…”

Section: Related Workmentioning

confidence: 99%

“…This has significant area and power overhead. Random Delay Insertion (Bucci et al, 2005;Strachacki and Szczepanski, 2008), where special flip-flops are inserted to interrupt the process throughout the data path. Most of the countermeasures concentrated on use of minimum signal strength and information (Boey et al, 2010;Mazumdar et al, 2012;Durga et al, 2013).…”

Section: Related Workmentioning

confidence: 99%

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A Defense Mechanism for Differential Power Analysis Attack in AES

Rajaram¹,

Vijaya²

2015

Journal of Computer Science

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Abstract:In modern wireless communication world, the security of data transfer has been the most challenging task. In embedded system, AES is the most extensively used cryptographic algorithm in practice. But its functionality has been disrupted by the DPA attack. There have been several countermeasures to tackle those attacks, but this study proposes variably a new measure to defend this DPA attack. DPA attack is possible due to the power fluctuation happening due to sequential circuit clocking during the process of substitute byte in AES encryption in the first round and last round. Hence to prevent this, the power variation is maintained at a constant pace throughout the data processing. This is achieved by incorporating a combinational logic design instead of a sequential logic circuit in AES. The proposed design is implemented in Vertex III FPGA device and found even after 17230 power traces the secret key is not disclosed as the power fluctuations is completely random. The power consumption when experimented by micro wind software proves to be constant and the same power (almost) is obtained while implementing it hardware and no chance of identifying the instant of data processing is achieved.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

A Defense Mechanism for Differential Power Analysis Attack in AES

Rajaram¹,

Vijaya²

2015

Journal of Computer Science

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“…More traces are need to distill the signal out of noise. Random delays can also be inserted at gate-level [5]. Dynamic frequency switching (DFS) [6] is another effective approach of hiding in the temporal dimension.…”

Section: Introductionmentioning

confidence: 99%

Enhance Multi-bit Spectral Analysis on Hiding in Temporal Dimension

Luo

2010

Lecture Notes in Computer Science

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Abstract. Random delays and dynamic frequency switching are widely adopted in smartcards and embedded systems as temporal hiding countermeasures to side channel attack.Temporal hiding is regarded as efficient to enhance the security of cryptographic devices. However, spectral analysis with Fast Fourier Transform is a powerful method to defeat temporal hiding countermeasures. Spectral analysis shares the same merit with integration different power attack. Multi-bit spectral analysis is enhanced with partitioning power analysis, which is much more effective than the correlation power analysis in the spectral domain. Multi-bit spectral analysis effectively defeats temporal hiding countermeasure with floatingmean dynamic frequency switching countermeasure. It is suggested cryptographic devices should employ other countermeasures together with hiding to ensure side channel security.

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“…Another common protection method is power trace misalignment, such as using a randomized clock [2], [8], [27], inserting random delays [4] and using multiple clock domains [9]. Randomized clock countermeasures use a single system clock which switches at random discrete time instants.…”

mentioning

confidence: 99%

“…Since these countermeasures do not change the overall power consumption behavior of the circuit, but only misaligns the power consumption traces, alignment preprocessing techniques such as elastic alignment [26] and rapid alignment method (RAM) [16] could be used to defeat such countermeasures. The random delay insertion method proposed by Bucci et al [4] uses random number of delay buffers after each memory element on the data path. Since this countermeasure uses single system clock for all memory elements, the power consumption caused by the memory elements at the clock switches, which usually dominates the overall consumption, is aligned and could be exploited by the attacker.…”

mentioning

confidence: 99%

An EDA-Friendly Protection Scheme against Side-Channel Attacks

Bayrak

Velickovic

Regazzoni

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-This paper introduces a generic and automated methodology to protect hardware designs from side-channel attacks in a manner that is fully compatible with commercial standard cell design flows. The paper describes a tool that artificially adds jitter to the clocks of the sequential elements of a cryptographic unit, which increases the non-determinism of signal timing, thereby making the physical device more difficult to attack. Timing constraints are then specified to commercial EDA tools, which restore the circuit functionality and efficiency while preserving the introduced randomness. The protection scheme is applied to an AES-128 hardware implementation that is synthesized using both ASIC and FPGA design flows.

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A Countermeasure against Differential Power Analysis based on Random Delay Insertion

Cited by 59 publications

References 15 publications

A Defense Mechanism for Differential Power Analysis Attack in AES

A Defense Mechanism for Differential Power Analysis Attack in AES

Enhance Multi-bit Spectral Analysis on Hiding in Temporal Dimension

An EDA-Friendly Protection Scheme against Side-Channel Attacks

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