A critical examination of 3D stackable NAND Flash memory architectures by simulation study of the scaling capability

Hsiao, Yi‐Hsuan; Lue, Hang-Ting; Hsu, Tzu-Hsuan; Hsieh, Kuang-Yeu; Lu, Chih‐Yuan

doi:10.1109/imw.2010.5488390

Cited by 57 publications

(27 citation statements)

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“…Several variants of oxide and even the combination with a metal gate and Hi-K could be employed in CT devices [5,10]. In 2D NAND, the basic cell structure is based on a floating gate (FG), where an insulated polysilicon structure between the gate and the channel, the FG, is used to store the electrons.…”

Section: The Storage Method: Transitioning From Floating Gate To Charmentioning

confidence: 99%

“…Several variants of oxide and even the combination with a metal gate and Hi-K could be employed in CT devices [5,10]. …”

Section: The Storage Method: Transitioning From Floating Gate To Charmentioning

confidence: 99%

“…Any local variation of the curvature of the cell structure may enhance the negative effects of an increased electric field, and this has also to be considered carefully. Therefore, in GAA cells, special attention must be paid to the design of the programming algorithms for reliable NAND operation [5].…”

Section: Transition To 3d Nandmentioning

confidence: 99%

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3D NAND Flash Based on Planar Cells

Silvagni¹

2017

Computers

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Abstract:In this article, the transition from 2D NAND to 3D NAND is first addressed, and the various 3D NAND architectures are compared. The article carries out a comparison of 3D NAND architectures that are based on a "punch-and-plug" process-with gate-all-around (GAA) cell devices-against architectures that are based on planar cell devices. The differences and similarities between the two classes of architectures are highlighted. The differences between architectures using floating-gate (FG) and charge-trap (CT) devices are also considered. Although the current production of 3D NAND is based on GAA cell devices, it is suggested that architectures with planar cell devices could also be viable for mass production.

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Section: The Storage Method: Transitioning From Floating Gate To Charmentioning

confidence: 99%

“…Several variants of oxide and even the combination with a metal gate and Hi-K could be employed in CT devices [5,10]. …”

Section: The Storage Method: Transitioning From Floating Gate To Charmentioning

confidence: 99%

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3D NAND Flash Based on Planar Cells

Silvagni¹

2017

Computers

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“…Moreover, most of them are not optimal in terms of bit density and bit cost, because of process issues such as the pipeline process, word line separation, and grain boundary limitation. In addition, minimum cell size is limited by the hole for the vertical channel with Poly-Si channel and surrounded ONO [8]. In this paper, we propose a scalable 3D NAND flash structure using fringing field in order to overcome scalability issues of conventional 3D NAND structures.…”

Section: Introductionmentioning

confidence: 99%

Programming Characteristics on Three-Dimensional NAND Flash Structure Using Edge Fringing Field Effect

Yang¹,

Song²

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The three-dimensional (3-D) NAND flash structure with fully charge storage using edge fringing field effect is presented, and its programming characteristic is evaluated. We successfully confirmed that this structure using fringing field effect provides good program characteristics showing sufficient threshold voltage (V T ) margin by technology computer-aided design (TCAD) simulation. From the simulation results, we expect that program speed characteristics of proposed structure have competitive compared to other 3D NAND flash structure. Moreover, it is estimated that this structural feature using edge fringing field effect gives better design scalability compared to the conventional 3D NAND flash structures by scaling of the hole size for the vertical channel. As a result, the proposed structure is one of the candidates of Terabit 3D vertical NAND flash cell with lower bit cost and design scalability.Index Terms-Novel 3D NAND flash structure, edge fringing field effect, scalability

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“…These advantages include lower programming voltage, superior programming/erasing speeds, and a simple fabrication process compatible with standard complementary metal-oxidesemiconductor technology [1][2][3]. Recently, CTF memory devices have gained increasing interest in the three dimensional (3D) integration for next generation nonvolatile memory technology [4,5]. The tunnel oxide thickness plays a crucial role in regulating the erasing speed, data retention characteristics and charge loss mechanisms for CTF memory devices [6], while the thickness of the nitride charge trapping layer is less critical.…”

Section: Introductionmentioning

confidence: 99%

Dependence of Electrons Loss Behavior on the Nitride Thickness and Temperature for Charge Trap Flash Memory Applications

Tang¹,

Ma²,

Zhang³

et al. 2014

Transactions on Electrical and Electronic Materials

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charge trap flash memory structures with various thicknesses of the Si 3 N 4 charge trapping layer were fabricated. According to the calculated and measured results, we depicted electron loss in a schematic diagram that illustrates how the trap to band tunneling and thermal excitation affects electrons loss behavior with the change of Si 3 N 4 thickness, temperature and trap energy levels. As a result, we deduce that Si 3 N 4 thicknesses of more than 6 or less than 4.3 nm give no contribution to improving memory performance.

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A critical examination of 3D stackable NAND Flash memory architectures by simulation study of the scaling capability

Cited by 57 publications

References 1 publication

3D NAND Flash Based on Planar Cells

3D NAND Flash Based on Planar Cells

Programming Characteristics on Three-Dimensional NAND Flash Structure Using Edge Fringing Field Effect

Dependence of Electrons Loss Behavior on the Nitride Thickness and Temperature for Charge Trap Flash Memory Applications

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