A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel

Bae, Jun-Hyun; Sohn, Young-Soo; Bae, Seung-Jun; Park, Kwang-Il; Choi, Joon-Ho; Jun, Young-Hyun; Sim, Jae‐Yoon; Park, Hong-June

doi:10.1109/cicc.2010.5617470

Cited by 3 publications

(1 citation statement)

References 5 publications

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“…The I/O Special Cell Library (IOSpCL) is built using 32/28nm 1P10M 1.05V/2.5V design rules with the same sized as standard I/O cells. The library includes I/Os complying to LPDDR [6], HSTL [7] and SSTL [8] standards.…”

Section: I/o Cell Librarymentioning

confidence: 99%

32/28nm Educational Design Kit: Capabilities, deployment and future

Goldman

Bartleson

Wood

et al. 2013

2013 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)

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An Educational Design Kit (EDK) which supports a 32/28nm design flow is described which includes all the necessary design rules, models, technology files, verification and extraction command decks, scripts, symbol libraries, and PyCells. It also includes a Digital Standard Cell Library (DSCL) which supports all contemporary low power design techniques; an Standard and Special I/O Cell Libraries (IOSCL and IOSpCL); a set of memories (SOM) with different word and data depths; a set of low-power memories (SOM LP) and a phase-locked loop (PLL).These components of the EDK augment any type of design for educational and research purposes. Though the EDK does not contain any foundry information, it allows 32/28nm technology with high accuracy close to real processes to be implemented in the designs

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Section: I/o Cell Librarymentioning

confidence: 99%