A Cu/low-κ dual damascene interconnect for high performance and low cost integrated circuits

Zhao, Bin; Feiler, D.; Ramanathan, Vidya; Liu, Q.Z.; Brongo, M.; Wu, J. Y.; Zhang, H.; Kuei, J.; Young, David; Brown, James Ward; Vo, Cong Phat; Xia, Weimin; Chu, Cao; Zhou, Jiechao; Nguyen, Cong Tien; Tsau, L.; Dornish, D.; Camilletti, Lawrence; Ding, Peng; Lai, Gigi; Chin, Barry L.; Johnson, Manoj; Turner, James A.; Ritzdorf, T.; Wu, G.; Cook, L.

doi:10.1109/vlsit.1998.689186

Cited by 10 publications

(6 citation statements)

References 4 publications

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“…At 250-nm technology node, copper (Cu) with low-dielectric was introduced to alleviate the adverse effect of increasing interconnect delay [14]- [18]. However, as shown in Fig.…”

Section: B Physical Limitations Of Cu Interconnectsmentioning

confidence: 99%

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

Banerjee¹,

Souri²,

Kapur³

et al. 2001

Proc. IEEE

903

411

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Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occupying a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with especial attention to SoC design strategies. Finally, some of the promising technologies for manufacturing 3-D ICs have been outlined.

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“…At 250-nm technology node, copper (Cu) with low-dielectric was introduced to alleviate the adverse effect of increasing interconnect delay [14]- [18]. However, as shown in Fig.…”

Section: B Physical Limitations Of Cu Interconnectsmentioning

confidence: 99%

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

Banerjee¹,

Souri²,

Kapur³

et al. 2001

Proc. IEEE

903

411

View full text Add to dashboard Cite

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“…12 Several papers have demonstrated the successful integration of both Al and Cu metals with low-dielectrics using damascene CMP. [13][14][15][16][17] In many strategies for damascene patterning, a hardmask or etch stop comprises the top tenth to fifth of the dielectric thickness to protect the dielectric from dry and wet etch chemistries. This hardmask, often silicon nitride or silicon oxide, has a higher dielectric constant (high-, 4.0 < < 7.0 ) than the low-material, resulting in a higher effective dielectric constant for the ILD stack.…”

mentioning

confidence: 99%

Chemical Mechanical Polishing Mechanisms of Low Dielectric Constant Polymers in Copper Slurries

Borst

Thakurta

Gill

et al. 1999

J. Electrochem. Soc.

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Chemical mechanical polishing (CMP) has emerged as a time, materials, and cost effective solution for providing the planar dielectric 1-3 and metal 4-8 layers necessary for the fabrication of sub-0.25 m interconnects. Present integrated circuit (IC) interconnects use aluminum lines, tungsten vias, and oxide interlevel dielectrics (ILDs). Advanced structures use copper lines and vias with low dielectric constant (low-) ILDs. Copper metal provides faster signal transfer and enhanced interconnect lifetime and low-ILDs (2.0 < < 3.0) reduce signal delay and cross-talk capacitance. [9][10][11] The fabrication of copper and low-interconnects requires copper patterning by damascene CMP. The single damascene process includes etching trenches or contact holes (vias) into the dielectric, filling these trenches with liner/barrier and metal, and removing the undesired metal from field regions using CMP. 12 Several papers have demonstrated the successful integration of both Al and Cu metals with low-dielectrics using damascene CMP. [13][14][15][16][17] In many strategies for damascene patterning, a hardmask or etch stop comprises the top tenth to fifth of the dielectric thickness to protect the dielectric from dry and wet etch chemistries. This hardmask, often silicon nitride or silicon oxide, has a higher dielectric constant (high-, 4.0 < < 7.0 ) than the low-material, resulting in a higher effective dielectric constant for the ILD stack. The CMP scheme illustrated in Fig. 1 allows the lowest capacitance from Cu/low-integration. The desired process requires removal of the copper metal overburden followed by removal of liner/hardmask materials from the dielectric surface. Processing in this manner results in direct CMP of the low-dielectric during the overpolishing required to ensure that all copper, barrier, and hardmask are completely removed.Polymeric and porous low-alternatives are, in general, not as strong physically as SiO 2 , although they are very stable chemically. Reduced physical strength and increased chemical resistance lead to challenges during CMP. The currently accepted mechanism for CMP is chemical alteration of a material surface followed by mechanical abrasion and removal. If relatively high-polish stops are to be polished away, the same slurry used for copper and barrier removal will contact the underlying polymer. Understanding the physical and chemical alteration of the low-material surface during copper CMP is of particular importance for creating electrically, thermally, chemically, and physically stable copper/low-interconnect structures. This information is of increasing importance for future technologies, particularly as minimum feature sizes go below 100 nm.The CMP of polyimide, 18 parylene-n, 19-21 BCB, 19-23 SiLK TM , 22,23 and FLARE TM 24 has been examined previously, in both damascene patterning and direct planarization strategies. The present work compares the CMP of BCB ( ϳ 2.65) and SiLK ( ϳ 2.65) polymer thin films in slurries developed for copper CMP. The effects of slurry chemistry and ab...

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“…Furthermore, the low dielectric properties can be achieved if the formation of -OH bonds and moisture absorption in the film is minimized [6]. Therefore, the integration of HSQ film as an IMD into multilevel interconnects has received much attention [7], [8]. However, the use of copper interconnects has some issues in integrated circuit (IC) application because it is easy for copper to diffuse into the dielectric films degrading the reliability [9].…”

Section: Introductionmentioning

confidence: 99%

Effects of NH/sub 3/-plasma nitridation on the electrical characterizations of low-k hydrogen silsesquioxane with copper interconnects

Liu

Chan

Yang

et al. 2000

IEEE Trans. Electron Devices

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The interaction between copper interconnects and low-hydrogen silsesquioxane (HSQ) film was investigated using a Cu/HSQ/Si metal insulation semiconductor capacitor and NH 3 plasma post-treatment. Owing to serious diffusion of copper atoms in HSQ film, degradations of the dielectric properties are significant with the increase of thermal stress. The leakage current behavior in high field conduction is well explained by the Poole-Frenkel (P-F) mechanism. By applying NH 3-plasma treatment to the HSQ film, however, the leakage current is decreased and P-F conduction can be significantly suppressed. In addition, the phenomenon of serious Cu penetration is not observed by means of electrical characteristic measurements and secondary ion mass spectroscopy (SIMS) analysis even in the absence of diffusion barrier layers. This indicates the copper diffusion in low-HSQ film can be effectively blocked by NH 3 plasma post-treatment.

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A Cu/low-κ dual damascene interconnect for high performance and low cost integrated circuits

Cited by 10 publications

References 4 publications

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

Chemical Mechanical Polishing Mechanisms of Low Dielectric Constant Polymers in Copper Slurries

Effects of NH/sub 3/-plasma nitridation on the electrical characterizations of low-k hydrogen silsesquioxane with copper interconnects

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