A current signal CMOS sample-and-hold circuit

Abstract

This article presents a current signal sample-and-hold (S/H) circuit using 0.5f.lm CMOS technology. A current minimum circuit is used to sample the input signal in place of a sampling switch used in the conventional S/H circuit. The current peak detector is used to hold the signal from the minimum circuit in the "hold" state. The proposed configuration is adopted effectively to cancel switch feedthrough error. The performances of the proposed circuit are demonstrated using the PSPICE analog simulation program. Simulation results show the sampling frequency up to 100MHz and high accuracy.

4th-Order Switched-Current Multistage-Noise-Shaping Delta-Sigma Modulator With a Simplified Digital Noise-Cancellation Circuit

“…Relative to a switched-capacitor circuit, a switched-current (SI) circuit performs better owing to its high speed, small chip area, and low supply voltage [9]. Unfortunately, an SI circuit can suffer from transmission errors, clock feedthrough (CFT) errors, nonlinearity, and high power consumption [10]. The CFT errors can be minimized by means of a current minimum function in place of a sampling switch [11].…”

“…,29,30) (25) S4 = Ʃm (0,2,5,7,8,10,13,15,17,19,20,22,25,27,28,30) (26)S3 = Ʃm (0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15) …”