A decimation filter architecture for GHz delta-sigma modulators

Kuskie, C.; Zhang, B.; Schreier, Richard

doi:10.1109/iscas.1995.519923

Cited by 4 publications

(3 citation statements)

References 7 publications

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“…Several different architectures have been proposed [1], [10], [11], [15]. Furthermore, using general FIR filters instead of CIC filters allows an arbitrary set of filter coefficients, optimized for a suitable cost function.…”

Section: Cic Filter Ismentioning

confidence: 99%

“…The examples are based on CIC filters due to their common use in Σ∆-converters, although it is possible to implement arbitrary FIR filters using the same approach. 4 In [1], [10], [11], [15], different methods of generating partial products for given filters were investigated.…”

Section: Cic Filter Ismentioning

confidence: 99%

“…Figure 11 shows the impact of the pipeline factor on the first filter with short wordlengths. For the 4-tap Fig 11 filter, N a = 1.8, and according to (15) utilizing the coefficient symmetry does not lead to reduced arithmetic complexity for w d < 2.25, and the DF2 architecture has thus not been included. Also, the half adder complexity was equal to 6 for all filters.…”

Section: E Constant Term Placementmentioning

confidence: 99%

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Integer Linear Programming-Based Bit-Level Optimization for High-Speed FIR Decimation Filter Architectures

Blad

Gustafsson

2009

Circuits Syst Signal Process

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Analog-to-digital converters based on sigma-delta modulation have shown promising performance, with steadily increasing bandwidth. However, associated with the increasing bandwidth is an increasing modulator sampling rate, which becomes costly to decimate in the digital domain. Several architectures exist for the digital decimation filter, and among the more common and efficient are polyphase decomposed FIR filter structures.In this paper, we consider such filters implemented with partial product generation for the multiplications, and carry-save adders to merge the partial products. The focus is on the efficient pipelined reduction of the partial products, which is done using a bit-level optimization algorithm for the tree design. However, the method is not limited only to filter design, but may also be used in other applications where high-speed reduction of partial products is required.The presentation of the reduction method is carried out through a comparison between the main architectural choices for FIR filters: the direct-form and transposed direct-form structures. For the direct-form structure, usage of symmetry adders for linear-phase filters is investigated, and a new scheme utilizing partial symmetry adders is introduced. The optimization results are complemented with energy dissipation and cell area estimations for a 90nm CMOS process.

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Section: Cic Filter Ismentioning

confidence: 99%