Integer Linear Programming-Based Bit-Level Optimization for High-Speed FIR Decimation Filter Architectures

Abstract

Analog-to-digital converters based on sigma-delta modulation have shown promising performance, with steadily increasing bandwidth. However, associated with the increasing bandwidth is an increasing modulator sampling rate, which becomes costly to decimate in the digital domain. Several architectures exist for the digital decimation filter, and among the more common and efficient are polyphase decomposed FIR filter structures.In this paper, we consider such filters implemented with partial product generation for the multiplications, and carry-save adders to merge the partial products. The focus is on the efficient pipelined reduction of the partial products, which is done using a bit-level optimization algorithm for the tree design. However, the method is not limited only to filter design, but may also be used in other applications where high-speed reduction of partial products is required.The presentation of the reduction method is carried out through a comparison between the main architectural choices for FIR filters: the direct-form and transposed direct-form structures. For the direct-form structure, usage of symmetry adders for linear-phase filters is investigated, and a new scheme utilizing partial symmetry adders is introduced. The optimization results are complemented with energy dissipation and cell area estimations for a 90nm CMOS process.

Study the Characteristics of FIR filter Based on Modified Kaiser Window

“…An adaptive analog filter is introduced based on echo cancelation [10]. An efficient pipelined filter is implemented using many structures [11]. A wideband efficient linear phase filter is implemented [12].…”

Adaptive window method of FIR filter design

“…Anton Blad et al are considered the FIR filter structures that implemented on the efficient pipelined high speed reduction of the moderate number of partial product. The algorithm was used to optimize filter realization using many architectures [5]. Raija Lehto et al are implemented a method to synthesize wide band linear phase FIR filters with a piecewise polynomial sinusoidal impulse response.…”

Efficient structural adder pipelining in transposed form FIR filters

“…Different methods have been proposed for the design of carry-save adder (CSA) based FIR filters, including the use of CSAs for structural adders [11], [12]. However, more adders are required compared to multiplier blocks designed by CPAs for word lengths of coefficients larger than 9 bits [12].…”