Efficient structural adder pipelining in transposed form FIR filters

Abstract

Pipelining is a common method to implement high speed FIR filters. While the efficient pipelining of multiplications is well understood, no attention has been paid on the pipelining of structural adders so far. The delay of structural adders becomes crucial in high speed designs as they have the largest word size in non-truncated FIR filters and typically lie in the critical path. The common pipelining method results in an excessive overhead in registers when applied to the structural adders as many additional paths have to be delayed. An efficient method for pipelining structural adders using a partially redundant number representation is proposed in this paper. With a very little area overhead of 5.4%, the throughput of the structural adders can be doubled while a speedup factor of up to 7 can be achieved with an area overhead of 26.7%.

Low Area VLSI implementation of CSLA for FIR Filter Design

“…Generally, there are two types of techniques, those are, Sparse FIR filters and multiplier fewer FIR filters, to design FIR filters that consume low power and hardware cost is less . An FIR filter in the transposed form can be classified into the algorithmic delay, SAs and multiplier block [6]. The arithmetic operators required more area which is the main limitations for designing a digital filter in the DSP system [7].…”