A deep sub-micron SRAM cell design and analysis methodology

The paper presents eight transistors SRAM cell with improved noise (interferences) immunity. The effect is reached by use an additional bus to control the state of the cell trigger. The results of the simulations as well as experiments have been demonstrated. The following SRAM characteristics have been obtained SNM = 222 mV, WRM = 1017 mV, the cell discharge current is 114 uA. The test chip has been fabricated with parameters of 180 nm CMOS process of UMC

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A two-input 8-transistor SRAM cell with enhanced noise immunity

Коротков

Morozov

Hauer

2016

2016 International Symposium on Fundamentals of Electrical Engineering (ISFEE)

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An SRAM weak cell fault model and a DFT technique with a programmable detection threshold

Pavlov

Sachdev

Gyvez

2004 International Conferce on Test

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SRAM cell stability has become an important design and test issue owing tu significant process spreads, non-ideal operational conditions, and subtle manufacturing defects in scaled-down geometries. In this article, we carry out an extensive SRAM SNM sensitivity analysis and propose an SRAM cell stability fault model for weak cell detection. This fault model is used fo design and veri& a proposed digitally pmgrammable design-for-test (DFI') technique targeting the weak cell detection in embedded SRAMs (eSRAM).

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A deep sub-micron SRAM cell design and analysis methodology

Cited by 2 publications

References 9 publications

A two-input 8-transistor SRAM cell with enhanced noise immunity

A two-input 8-transistor SRAM cell with enhanced noise immunity

An SRAM weak cell fault model and a DFT technique with a programmable detection threshold

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