The 20th Asia and South Pacific Design Automation Conference 2015
DOI: 10.1109/aspdac.2015.7058991
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A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays

Ching-Yi Huang
1
,
Chian-Wei Liu
2
,
Chun-Yao Wang
3
et al.
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Cited by 4 publications
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Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays

Wu
1
,
Ho2,
Huang
3
et al. 2018
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
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Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays

Wu
1
,
Ho2,
Huang
3
et al. 2018
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
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Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays

Huang
1
,
Li
2
,
Liu
3
et al. 2016
IEEE Trans. VLSI Syst.
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Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays

Li
1
,
Huang
2
,
Wu
3
et al. 2017
IEEE Trans. VLSI Syst.
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