Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays

Huang, Ching-Yi; Li, Yun-Jui; Liu, Chian-Wei; Wang, Chun-Yao; Chen, Yung-Chih; Datta, Suman; Narayanan, Vijaykrishnan

doi:10.1109/tvlsi.2015.2506780

Cited by 4 publications

(3 citation statements)

References 19 publications

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“…Additionally, [11] proposed an error injection method in their work to generate incorrect SET array implementations for demonstrating that the proposed verification method also works for incorrect SET array implementations as well. Later, [27] presented a diagnosis methodology to specify the defects in SET arrays by two defect‐aware algorithms for mapping SET arrays. In fact, the error injection method is not part of [11], it will be totally unpredictable and can alter the SET structure and the verification time tremendously based on where you inject the error.…”

Section: Automatic Tool and Experimental Resultsmentioning

confidence: 99%

“…Future work can be directed towards advances in integrated circuit technology and verification techniques. More research is required to explore SET array‐based design synthesis and verification [27]. In addition, using the abstraction power of MDGs, the work can be extended to include abstract terms.…”

Section: Discussionmentioning

confidence: 99%

“…Several authors were able to automatically extract the formal mathematical model from the design specification [26]. Similarly, extracting a DF model from the behavioural design is based on the rules explained in [26,27]. CNFFormulaConstraints = ConvertToCNF(BoolFormulaConstraints);…”

Section: Generation Cnf From Dfmentioning

confidence: 99%

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Automatic verification of single‐electron transistor arrays based on multiway decision graphs

Abed

Ahmad

Shayeji

et al. 2017

IET Circuits, Devices & Systems

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The single-electron transistor (SET) is considered as a promising alternative to CMOS devices and integrated circuits due to its ultra-low-power consumption. The authors propose an automatic methodology by utilising SET-based multiway decision graph (MDG) for implementing SET architecture. MDG provides a powerful means of abstraction and can be used to manipulate a certain type of first-order logic formula called directed formula (DF). An automatic tool has been developed that is capable of transferring the SET array into MDG DF to generate all paths of all possible reachable states, drawing an abstract diamond-shaped network for the SET array, producing a reduced DF generated by the MDG tool and converting the reduced DF into a conjunctive normal form formula. Then, the authors use the satisfiability approach as a verification engine to verify the correctness of these conversions. The method is tested and verified using MCNC benchmarks. The results outperform approaches based on binary decision diagrams in terms of verification time, number of clauses and variables.

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Section: Automatic Tool and Experimental Resultsmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%