A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability

Abstract

As the demand of safety-critical applications (e.g., automobile electronics) increases, various radiation-hardened flip-flops are proposed for enhancing design reliability. Among all flip-flops, Delay-Adjustable D-Flip-Flop (DAD-FF) is specialized in arbitrarily adjusting delay in the design to tolerate soft errors induced by different energy levels. However, due to a lack of testability on DAD-FF, its soft-error tolerability is not yet verified, leading to uncertain design reliability. Therefore, this work proposes Delay-Adjustable, Self-Testable Flip-Flop (DAST-FF), built on top of DAD-FF with two extra MUXs (one for scan test and the other for latching-delay verification) to achieve both soft-error tolerability and testability. Meanwhile, a built-in self-test method is also developed on DAST-FFs to verify the cumulative latching delay before operation. The experimental result shows that for a design with 8,802 DAST-FFs, the built-in self-test method only takes 946 ns to ensure the soft-error tolerability. As to the testability, the enhanced scan capability can be enabled by inserting one extra transmission gate into DAST-FF with only 4.5 area overhead.

A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design

“…An erroneous change of the state held in a storage cell caused by a particle strike is called Single event upset (SEU), which is the key contributor to the overall system soft error rate in modern VLSI circuits [4]. The SEU robustness of flip-flops is essential to ensure the overall reliability since flip-flop is one of the major elements in many digital designs [5,6]. Radiation Hardening by Design (RHBD) is an important technique to mitigate SEU in flip-flops as it works in commercial CMOS technology with no violation of design rules.…”