A delay model for logic synthesis of continuously-sized networks

Abstract

model will enable us to use a modified tree-mapping technology to efficiently produce continuously-sized netlists satisfying certain electrical noise and power constraints. Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as constant and makes the cell's delay a linear function of load. Our model is based on a different, but equally fundamental linearity in the equation relating area, delay, and load: namely, we may keep a cell's delay constant by making its area a linear function of load. This allows us to technology map using a library with continuous device sizing, satisfies certain electrical noise and power constraints, and in certain cases is computationally simpler than a traditional model. We give results to support these claims. A companion paper [14] uses the computational simplicity to explore a wide search space of algebraic factorings in a mapped network.Our own application is for continuously-sized, fullcustom designs. However, the delay model is also applicable to other methodologies, such as high-end standard cell, where there are many sizes of each cell. Essentially, it applies to any technology where cell sizing to obtain a desired delay is viable.Constant-delay modeling has been used frequently in technology-independent algorithms. For example, Wang [15,pg.167] proposed decomposing a network into bounded-fanin NAND gates, assigning a unit delay to each level of logic, and determining and restructuring critical regions with the resulting arrival times.Singh [12, pp.13-19] has measured the accuracy of various technology-independent delay models. He concluded that the unit-delay model on bounded-fanin gates was the most accurate. His speedup[8] made technology-independent decomposition decisions by first breaking down the network into two-input NAND gates, and then modeling each NAND gate as a unit delay. Introduction.Most technology mapping algorithms for logic synthesis have been targeted at technologies with a limited number of cell sizes. A straightforward modeling technique will then model each library element with a unique cell, whose area is fixed and whose delay varies with output loading. A class of technology-mapping algorithms called tree-mapping [1,2,3] is well suited to such a model. Given a tree-structured network and a fixed cell library, tree-mapping algorithms run in time linear in the number in the number of circuit nodes. They are also linear in the number of library cells, which is of course not a problem for these reasonably-small libraries.

A Design Flow for Performance Planning: New Paradigms for Iteration Free Synthesis

“…The important observation is that r can be kept constant by fixing f = C~~/ CL. This leads to a new paradigm in synthesis [8,18]: any delay imposed by syn thesis can be realized, provided that the sizes of the gates can be continuously adjusted, and the imposed delay exceeds the parasitic delay. Note however that the derivation replaced the gate by a single linear "effective" resistance and a linear input and drain capacitance.…”

“…Layout synthesis should produce a network in which each gate causes exactly that delay. This is called constant delay synthesis [8]. Given a fixed delay for a gate, its size becomes a function of the output capacitance.…”

“…For more general charge or discharge networks of mos-transistors a single sizing factor can be derived [8]:…”

Logical effort based technology mapping

“…In the matching step, matches for all gates are generated, and the optimum match at each gate is stored as the solution for that gate, and in the covering step, the solution for the entire circuit is generated by an outputto-input traversal. Later approaches [3,4,5] improve on [1] by using more refined delay models that take into account the delay dependence of load, and the effect of multiple gate sizes. However, they do not address the load-distribution problem, described below.…”

“…A number of algorithms have been proposed for this step, such as tree-mapping [1] and DAG-mapping [2], using load-dependent delay models [3], constant delay models [4,5] as well as using logical effort [6]. High-performance designs use rich libraries, with multiple instances of each cell, with varying delay, area and drive capabilities.…”