A Design Flow for Performance Planning: New Paradigms for Iteration Free Synthesis

Abstract

Abstract. In conventional design, higher levels of synthesis produce a netlist, from which layout synthesis builds a mask specification for manufacturing. Timing anal ysis is built into a feedback loop to detect timing violations which are then used to update specifications to synthesis. Such iteration is undesirable, and for very high performance designs, infeasible. The problem is likely to become much worse with future generations of technology. To achieve a non-iterative design flow, early synthesis stages should use wire planning to distribute delays over the functional elements and interconnect, and layout synthesis should use its degrees of freedom to realize those delays.

Automatic layout design for power module

“…The purpose of VLSI design is to embed an abstract circuit description, such as a netlist, into silicon, creating a detailed geometric layout on a die [10,11]. As semiconductor fabrication processes improved, automation was facilitated by an improvement in the speed of computers that would be used to create new generations of chips, resulting in their own replacement [12,13].…”