A Design and Implementation of Reconfigurable Architecture for Neural Networks Based on Systolic Arrays

Qin, Wang; Li, Ang; Li, Zhancai; Wan, Yong

doi:10.1007/11760191_193

Cited by 7 publications

(3 citation statements)

References 6 publications

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“…In this way the same architecture can be used for several applications, making it more attractive for a real implementation, not only for nanotechnologies but also in CMOS. Some reconfigurable SAs have been proposed in recent years: the work in [23] presents a reconfigurable architecture for VLSI implementation of BP neural networks with on-chip learning, while in [24] a general purpose architecture for the parallelization of nested loops in reconfigurable architectures is described. Both SAs propose reconfigurability to address a specific problem's scale.…”

Section: Systolic Arraysmentioning

confidence: 99%

Reconfigurable Systolic Array: From Architecture to Physical Design for NML

Causapruno

Riente

Turvani

et al. 2016

IEEE Trans. VLSI Syst.

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NanoMagnet Logic (NML) is among the emerging technologies that might replace CMOS in next decades. According to its physical characteristics, to better exploit the potential of this technology -and of other similar ones -the use of parallel architectures with regular layout that avoid long interconnection signals is advised. Systolic Arrays are among these architectures, being composed of a grid of equal Processing Elements locally interconnected. However, they are usually implemented to execute only a small set of algorithms, and for this reason throughout the years they have not been an appealing solution for CMOS.To seriously analyze the potentials of NML, complex architectures must be conceived, and their physical implementation explored taking into account realistic technological constraints. With the increasing complexity of NML circuits, two issues, then, are noticed: 1) The need for a regular structure arises, that at the same time helps to reduce the intrinsic pipelining nature of NML and can be configured to be used for several applications without developing a dedicated design for each algorithm. 2) The capability to synthesize, place and route NML circuits is fundamental to demonstrate the feasibility of the architecture in two important conditions: efficiently managing the complexity of the design and sticking to the characteristics that are technologically feasible at the time of writing. In this article we address these issues presenting a new Reconfigurable Systolic Array, that can be programmed to execute different algorithms, and we provide two examples to show its working principle. Moreover the Array is synthesized and simulated with the aid of the first real tool for nanotechnology circuits that we have conceived, ToPoliNano. The joint contribution at both architectural and physical design level gives a relevant step forward to the state of the art in the demonstration of this emerging technology potential.

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Section: Systolic Arraysmentioning

confidence: 99%

Reconfigurable Systolic Array: From Architecture to Physical Design for NML

Causapruno

Riente

Turvani

et al. 2016

IEEE Trans. VLSI Syst.

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“…Aibe, et al [19]implemented a probabilistic neural network (PNN) Wang, et al [22] proposed a re-configurable architecture for the VLSI implementation of the BP algorithm based on systolic fields.…”

Section: Related Workmentioning

confidence: 99%

The Impact of Data Representationson Hardware Based MLP Network Implementation

2014

APH

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Artificial neural networks are massively parallel systems containing large amounts of simple computing elements. Therefore, it is natural to try to implement them using parallel computing architectures. This paper deals with an implementation of a three layer multilayer perceptron artificial neural network. It summarises the impact of using various forms of data representation on the performance of the hardware implementationa Kintex-7 XC7K325T-2FFG900C FPGA chip on a Xilinx Kintex KC705 board.

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“…The digital hardware implementation method was discussed deeply due to high precision, good expansibility and a good design support by EDA tools [5]. The common digital implementation architectures include systolic array architecture, slice architecture, Single Instruction Multiple Data (SIMD), and so on [6][7][8]. A Point-To-Point (P2P) data transmission is usually used by the digital implementation method.…”

Section: Introductionmentioning

confidence: 99%

Multiple Network-on-Chip Model for High Performance Neural Network

Dong¹,

Li²,

Lin³

et al. 2010

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Hardware implementation methods for Artificial Neural Network (ANN) have been researched for a long time to achieve high performance. We have proposed a Network on Chip (NoC) for ANN, and this architecture can reduce communication load and increase performance when an implemented ANN is small. In this paper, a multiple NoC models are proposed for ANN, which can implement both a small size ANN and a large size one. The simulation result shows that the proposed multiple NoC models can reduce communication load, increase system performance of connection-per-second (CPS), and reduce system running time compared with the existing hardware ANN. Furthermore, this architecture is reconfigurable and reparable. It can be used to implement different applications of ANN.

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A Design and Implementation of Reconfigurable Architecture for Neural Networks Based on Systolic Arrays

Cited by 7 publications

References 6 publications

Reconfigurable Systolic Array: From Architecture to Physical Design for NML

Reconfigurable Systolic Array: From Architecture to Physical Design for NML

The Impact of Data Representationson Hardware Based MLP Network Implementation

Multiple Network-on-Chip Model for High Performance Neural Network

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