A design for a minimum Hamming-distance search using asynchronous digital techniques

Nakahara, S.; Kawata, Tsunehiro

doi:10.1109/jssc.2004.837966

Cited by 6 publications

(3 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The accumulator is in charge of doing the sums of coherent samples as expressed in (12). Since the accumulation is complex, the I and Q branches each have their own accumulator.…”

Section: Fig 4 Constellation Locker Componentsmentioning

confidence: 99%

“…The 802.15.4 decorrelator uses a group of 16 comparators that calculate the hamming distance to each of the 16 possible symbols, the correct bits in each symbol are sorted using the method described in [12] that uses a leading ones sorting mechanism to simplify the process of finding the symbol that has the smallest hamming distance. The next step in the reception process is the descrambler.…”

Section: Fig 4 Constellation Locker Componentsmentioning

confidence: 99%

See 1 more Smart Citation

An FPGA-based all-digital 802.11b & 802.15.4 receiver for the Software Defined Radio paradigm

Espinoza-Rhoton

Gonzalez-Perez

Ponce

et al. 2014

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)

View full text Add to dashboard Cite

An FPGA implementation of an all-digital fully compliant IEEE 802.11b and 802.15.4 configurable baseband receiver is presented. This architecture can be integrated in systems implementing the Software Defined Radio (SDR) paradigm, relaxing the need for high power consumption general purpose processors. The receiver uses a single architecture that can be configured for receiving either standard at run time, exploiting similarities between both protocols, and may serve as a coprocessor for offloading the task of processing baseband RF signals. The system can be used as a platform for future low power devices to integrate into the SDR paradigm. Results showed that the architecture exceeds the specifications required by both standards, and has great performance in low SNR scenarios, making it an attractive alternative in wireless sensor networks with extremely low signal power levels.

show abstract

“…The accumulator is in charge of doing the sums of coherent samples as expressed in (12). Since the accumulation is complex, the I and Q branches each have their own accumulator.…”

Section: Fig 4 Constellation Locker Componentsmentioning

confidence: 99%

Section: Fig 4 Constellation Locker Componentsmentioning

confidence: 99%

An FPGA-based all-digital 802.11b & 802.15.4 receiver for the Software Defined Radio paradigm

Espinoza-Rhoton

Gonzalez-Perez

Ponce

et al. 2014

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)

View full text Add to dashboard Cite

show abstract

“…The minimum distance search needs two basic operations, namely distance calculation and distance comparison. As a means to realize associative memories with fully parallel search capability, digital system realizations 4,5) and combined digital-analog realizations [6][7][8] have been proposed. The previously proposed digital-analog associative memories achieve lower area consumption, lower power dissipation and faster search compared with the digital associative memories by mapping pattern distances into analog signals like current or voltage.…”

Section: Introductionmentioning

confidence: 99%

High Speed Frequency-Mapping-Based Associative Memory Using Compact Multi-Bit Encoders and a Path-Selecting Scheme

Sasaki¹,

Yasuda²,

Kawabata³

et al. 2012

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

A compact multi-bit encoding concept for nearest-distance search-speed improvement of scalable and reliable associative-memories utilizing a mapping operation of the distances into frequency space is reported. The distance differences are transformed into signal delays which are finally detected with a time-domain winner-take-all (WTA) circuit. Ring oscillators programmable in discrete frequency steps are used for the distance–frequency mapping. This implementation enables to decrease the effects of process-induced variations, because the step size is a constraint-free design parameter. To further improve the search reliability, frequency dividers are used to enlarge the size of the frequency steps. The multi-bit encoder achieves a substantial search-time reduction by optimizing the basic-ring oscillator delay for distance zero with a path-selecting scheme. The proposed multi-bit encoding concept has been evaluated with two test-chip designs in 180 nm complementary metal oxide semiconductor (CMOS) technology. Search-time reductions by a factor 1.7 in typical search cases and a compact circuit implementation are verified.

show abstract

Low-power word-parallel nearest-Hamming-distance search circuit based on frequency mapping

Mattausch

Imafuku

Ansari

et al. 2010

2010 Proceedings of ESSCIRC

View full text Add to dashboard Cite

A design for a minimum Hamming-distance search using asynchronous digital techniques

Cited by 6 publications

References 11 publications

An FPGA-based all-digital 802.11b & 802.15.4 receiver for the Software Defined Radio paradigm

An FPGA-based all-digital 802.11b & 802.15.4 receiver for the Software Defined Radio paradigm

High Speed Frequency-Mapping-Based Associative Memory Using Compact Multi-Bit Encoders and a Path-Selecting Scheme

Low-power word-parallel nearest-Hamming-distance search circuit based on frequency mapping

Contact Info

Product

Resources

About