A Design for Clock Synchronization Using CPPLL

Wang, Xiao; Zeng, Zhi Bin

doi:10.4028/www.scientific.net/amm.543-547.558

Cited by 2 publications

(3 citation statements)

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“…First-order controlled autonomous clock synchronization has already been studied in simulations and experiments in [18] by pointing out the unfitness of some other clock synchronization methods [12][13][14][15] for power packet dispatching. Based on the principle of the CPPLL, the model of a digital clock synchronization method is expressed in Eq.…”

Section: First-order Controlled Clock Synchronizationmentioning

confidence: 99%

“…For example, the charge-pump phase-locked loop (CPPLL) is a typical clock synchronization method with analog charging and filtering part, as in [15]. For example, the charge-pump phase-locked loop (CPPLL) is a typical clock synchronization method with analog charging and filtering part, as in [15].…”

Section: Introductionmentioning

confidence: 99%

“…Given the inapplicability of the external clock line in achieving clock synchronization, the selftiming clock synchronization methods were studied. For example, the charge-pump phase-locked loop (CPPLL) is a typical clock synchronization method with analog charging and filtering part, as in [15]. The CPPLL synchronizes the voltage-controlled oscillator output frequency to the input reference frequency through feedback.…”

Section: Introductionmentioning

confidence: 99%

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Power packet dispatching with second‐order clock synchronization

Zhou

Takahashi

Fujii

et al. 2015

Circuit Theory & Apps

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Aiming to distinguish sources and loads for the rapid scaling of renewable power sources, a novel power packet dispatching system has been proposed with a structure similar to those of communication systems. Accurate clock synchronization is necessary to achieve the exchange of information attached in a power packet. At the same time, the clock synchronization is an interesting topic for developing power packet dispatching between multi-sender and a receiver. This work outlines the implementation of second-order autonomously controlled clock synchronization into the power packet dispatching system. At first, we derive the second-order controlled model of a digital clock synchronization method and analyze the stability of the developed model. Secondly, through experiments, it is shown that the information of power packets can be recognized correctly and the power can be distributed to directed loads. This paper demonstrates the validity of the asynchronous power packet dispatching based on our derived model. k ð Þ NCO denotes the clock period of NCO. In Eq. (1), k indicates the serial number of reference clock cycle, and Δ(k) represents the phase difference between the two clock signals. We define Δ(k) > 0 if REF leads NCO, Δ(k) < 0 if REF lags NCO, and Δ(k) = 0 when REF and NCO are synchronized. t k indicates the start time of the k-th reference clock cycle. Here, the clock synchronization between REF and NCO means T k ð Þ NCO ¼ T REF , and thus, from Eq. (1), it is clear that the achievement of clock SECOND-ORDER CLOCK SYNCHRONIZATION 731 a 2 is also a constant parameter, which is taken to be positive. By substituting Eqs. (A3) and (A4) into Eq. (A2), the second-order controlled model can be obtained, SECOND-ORDER CLOCK SYNCHRONIZATION 741

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